Specifications

PL 3120/PL 3150/ PL 3170 Power Line Smart Transceiver Data Book 101
The hardware update does not happen until the occurrence of an external active sync clock edge. The internal timer is
then enabled and a triac gate pulse is generated after the user-defined period has elapsed. This sequence is repeated
indefinitely until another update is made to the triac gate pulse delay value.
t
fout
(min) refers to the delay from the initiation of the function call to the first sampling of the sync input. In the
absence of an active sync clock edge, the input is repeatedly sampled for 10ms (1/2 wave of a 50Hz line cycle
time), t
fout
(max), during which the application processor is suspended.
The output gate pulse is gated by an internal clock with a constant period of 25.6µs at 10MHz (39.062µs at
6.5536MHz). because the input trigger signal (zero crossing) is asynchronous relative to this internal clock, there
is a jitter, t
jit
, associated with the output gate pulse.
The actual active edge of the sync input and the triac gate output can be set by using the clockedge or invert
parameters, respectively.