Specifications

Chapter 3 – Input/Output Interfaces
100 PL 3120/PL 3150/PL 3170 Power Line Smart Transceiver Data Boo
k
A disabled output is a logic 0 by default unless the invert keyword is used in the I/O object declaration.
Triac Output
On the PL Smart Transceiver, a timer/counter can be configured to control the delay of an output signal with respect to a
synchronization input. This synchronization can occur on the rising edge, the falling edge, or both the rising and falling
edges of the input signal. For control of AC circuits using a triac device, the sync input is typically a zero-crossing
signal, and the pulse output is the triac trigger signal. Table 3.8 shows the resolution and maximum range of the delay
(see Figure 3.55).
The output gate pulse is gated by an internal clock with a constant period of 25.6µs at 10MHz (39.062µs at
6.5536MHz). because the input trigger signal (zero crossing) is asynchronous relative to this internal clock, there
is a jitter, t
jit
, associated with the output gate pulse.
The actual active edge of the sync input and the triac gate output can be set by using the clockedge or invert
parameters, respectively.
trigger
output
Timer/Counter 1
Timer/Counter 2
sync
IO0
IO1
IO2
IO3
IO4
IO5
IO6
IO7
mux
to
triac
gate
from
zero
crossing
detector
System Clock
Divide Chain
IO10
IO9
IO8
t
ret
END OF
io_out()
t
gpw
NEW
GATE-PULSE
DELAY
FIRST GATE
PULSE WITH
NEW DELAY
HARDWARE
UPDATED
START
OF
io_out()
TIME
TRIAC
GATE
(OUTPUT)
ZERO
CROSSING
DETECTOR
AC
INPUT
CLOCK EDGE
(+) or (-)
t
ret
END OF
io_out()
NEW
GATE-PULSE
DELAY
FIRST GATE
PULSE WITH
NEW DELAY
HARDWARE
UPDATED
START
OF
io_out()
TIME
TRIAC GATE
(OUTPUT)
ZERO
CROSSING
DETECTOR
AC
INPUT
CLOCK EDGE
(+-)
High Current Sink Drivers
t
jit
Optional Pull-Up Resistors
IO11
t
fout
t
jit
t
gpw
t
fout
Figure 3.55 Triac Output Latency Values