Specifications

Interface Specifics 55
Bus Controllers
The PC-Bus and Micro Channel SmartSet controllers use read/write I/O ports for
communicating the eight-byte packet.
Base I/O Port
The Base I/O Port is the location of first I/O port through which the controller and
the host exchange data. The Base I/O Port is selected from jumpers or NVRAM
with the E271-2201 PC-Bus controller, and through "automatic configuration"
with the E271-2202 Micro Channel controller. For more information on Base I/O
Port selection, see Chapter 2.
A block of eight consecutive ports are used for the eight-byte packet. They are
denoted as "Base Port", "Base Port + 1", etc., through "Base Port + 7".
To receive a packet from the controller, the host reads the eight I/O ports in
ascending order starting with the Base Port. The controller senses the completion
of the transfer when all eight ports have been read.
To send a packet to the controller, the host writes to the same eight I/O ports in
ascending order starting with the Base Port. The controller processes the
command after all eight ports have been written. A command received by the
controller takes priority over any background processing. This includes the
processing of another command. Therefore, the host must wait for an
Acknowledge response before issuing another command.
The controller informs the host that data is available by clearing a status bit and
optionally asserting an interrupt request line (IRQ). This allows the host driver
software to be polled or interrupt-driven.
Polled Mode
Polled Mode is commonly used in computer systems which do not have a
hardware interrupt signal available to assign to the touchscreen controller. Polled
drivers are easier to write but do not allow multi-tasking or event-driven
programming. (Elo drivers are interrupt-driven).
Bit 7 of the Base Port (the command byte), is the Not Ready bit. If the host is
polling the controller, it should wait until the Not Ready bit is 0 before reading the
remaining bytes. This negative logic is used so bit 7 does not need to be cleared in
response packets before they are resent to the controller as set commands. It also
makes packets received from bus controllers identical to those received from serial
controllers.