Datasheet

M2Y2G64CB8HC5N / M2Y2G64CB8HC9N
2GB: 256M x 64
Unbuffered DDR3 SDRAM DIMM
REV 1.1 12
01/2010
© NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
AC Timing Specifications for DDR3 SDRAM Devices Used on Module
DDR3-1066
DDR3-1333
Parameter
Symbol
Min
Max
Min
Max
Units
Clock Timing
Minimum Clock Cycle time (DLL off mode)
tCK(DLL_O
FF)
8
-
8
ns
Average high pulse width
tCH(avg)
0.47
0.53
0.47
0.53
tCK(avg)
Average low pulse width
tCL(avg)
0.47
0.53
0.47
0.53
tCK(avg)
Absolute Clock Period
tCK(abs)
tCK(avg)min
+tJIT(per)min
tCK(avg)max
+tJIT(per)max
tCK(avg)min
+tJIT(per)min
tCK(avg)max
+tJIT(per)max
ps
Absolute clock high pulse width
tCH(abs)
0.43
-
0.43
-
ps
Absolute clock low pulse width
tCL(abs)
0.43
-
0.43
-
ps
Clock Period Jitter
tJIT(per)
-90
90
-80
80
ps
Clock Period Jitter during DLL locking period
tJIT(per,lck)
-80
80
-70
70
ps
Cycle to Cycle Period Jitter
tJIT(cc)
180
160
ps
Cycle to Cycle Period Jitter during DLL locking period
tJIT(cc,lck)
160
140
ps
Duty Cycle Jitter
tJIT(duty)
-
-
-
-
ps
Cumulative error across 2 cycles
tERR(2per)
-132
132
-118
118
ps
Cumulative error across 3 cycles
tERR(3per)
-157
157
-140
140
ps
Cumulative error across 4 cycles
tERR(4per)
-175
175
-155
155
ps
Cumulative error across 5 cycles
tERR(5per)
-188
188
-168
168
ps
Cumulative error across 6 cycles
tERR(6per)
-200
200
-177
177
ps
Cumulative error across 7 cycles
tERR(7per)
-209
209
-186
186
ps
Cumulative error across 8 cycles
tERR(8per)
-217
217
-193
193
ps
Cumulative error across 9 cycles
tERR(9per)
-224
224
-200
200
ps
Cumulative error across 10 cycles
tERR(10per)
-231
231
-205
205
ps
Cumulative error across n=11~50 cycles
tERR(nper)
tERR(npr)min
=(1+0.68In(n))*tJIT
(per)min
tERR(npr)max
=(1+0.68In(n))*tJIT
(per)max
tERR(npr)min
=(1+0.68In(n))*tJIT
(per)min
tERR(npr)max
=(1+0.68In(n))*tJIT
(per)max
ps
Data Timing
DQS,  to DQ skew, per group, per access
tDQSQ
-
150
-
125
ps
DQ output hold time from DQS, 
tQH
0.38
-
0.38
tCK(avg)
DQ low-impedance time from CK, 
tLZ(DQ)
-600
300
-500
250
ps
DQ high-impedance time from CK, 
tHZ(DQ)
-
300
-
250
ps
Data setup time to DQS,  reference to Vih(ac) / Vil(ac)
levels
tDS(base)
AC175
25
-
-
-
ps
Data hold time to DQS,  reference to Vih(ac) / Vil(ac)
levels
tDS(base)
AC150
75
-
30
-
ps
Data hold time from DQS, referenced to Vih(dc) / Vil(dc)
levels
tDH(base)
DC100
100
65
ps
DQ and DM Input pulse width for each input
tDIPW
490
-
400
-
ps
Data Strobe Timing
DQS,  differential READ Preamble
tRPRE
0.9
-
0.9
-
tCK(avg)
DQS,  differential READ Postamble
tRPST
0.3
-
0.3
-
tCK(avg)
DQS,  differential output high time
tQSH
0.38
-
0.40
-
tCK(avg)
DQS,  differential output low time
tQSL
0.38
-
0.40
-
tCK(avg)
DQS,  differential WRITE Preamble
tWPRE
0.9
-
0.9
-
tCK(avg)
DQS,  differential WRITE Postamble
tWPST
0.3
-
0.3
-
tCK(avg)
DQS,  rising dege output access time from rising CK,

tDQSCK
-300
300
-255
255
ps
DQS,  low-impedance time (Reference from RL-1)
tLZ(DQS)
-600
300
-500
250
ps
DQS,  high-impedance time (Reference from RL +
BL/2)
tHZ(DQS)
-
300
-
250
ps
DQS,  differential input low pulse width
tDQSL
0.45
0.55
0.45
0.55
tCK(avg)
DQS,  differential input high pulse width
tDQSH
0.45
0.55
0.45
0.55
tCK(avg)