Datasheet

M2Y51H64TU88D0B / M2Y51H64TU88D6B / M2Y1GH64TU8HD0B / M2Y1GH64TU8HD6B
512MB: 64M x 64 / 1GB: 128M x 64
Unbuffered DDR2 SDRAM DIMM Preliminary Edition
REV 0.1 14
08/2008
© NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
AC Timing Specifications for DDR2 SDRAM Devices Used on Module
(T
CASE
= 0 °C ~ 85 °C; V
DDQ
= 1.8V ± 0.1V; V
DD
= 1.8V ± 0.1V, See AC Characteristics) (Part 1 of 2)
Symbol
Parameter
PC2-5300
PC2-6400
Unit
Min.
Max.
Min.
Max.
tAC
DQ output access time from CK/
-0.45
+0.45
-0.40
+0.40
ns
tDQSCK
DQS output access time from CK/
-0.40
+0.40
-0.35
+0.35
ns
tCH
CK high-level width
0.45
0.55
0.45
0.55
tCK
tCL
CK low-level width
0.45
0.55
0.45
0.55
tCK
tHP
Minimum half clk period for any given cycle;
defined by clk high (tCH) or clk low (tCL) time
tCH
or
tCL
-
tCH
or
tCL
-
tCK
tCK
Clock Cycle Time
3
8
2.5
8
ns
tDS
DQ and DM input setup time(differential data
strobe)
0.1
-
0.05
-
ns
tDH
DQ and DM input hold time(differential data strobe)
0.175
-
0.125
-
ns
tIPW
Input pulse width
0.6
-
0.6
-
tCK
tDIPW
DQ and DM input pulse width (each input)
0.35
-
0.35
-
tCK
tHZ
Data-out high-impedance time from CK/
-
tACmax
-
tACmax
ns
tLZ(DQS)
DQS low-impedance time from CK/
tACmin
tACmax
tACmin
tACmax
ns
tLZ(DQ)
DQ low-impedance time from CK/
2t
AC
min
t
AC
max
2t
AC
min
t
AC
max
ns
tDQSQ
DQS-DQ skew (DQS & associated DQ signals)
-
0.24
-
0.20
ns
tQHS
Data hold Skew Factor
-
0.34
-
0.3
ns
tQH
Data output hold time from DQS
tHP -
tQHS
-
tHP -
tQHS
-
ns
tDQSS
Write command to 1st DQS latching transition
-0.25
+0.25
-0.25
+0.25
tCK
tDQSL,(H)
DQS input low (high) pulse width
(write cycle)
0.35
-
0.35
-
tCK
tDSS
DQS falling edge to CK setup time
(write cycle)
0.2
-
0.2
-
tCK
tDSH
DQS falling edge hold time from CK
(write cycle)
0.2
-
0.2
-
tCK
tMRD
Mode register set command cycle time
2
-
2
-
tCK
tWPST
Write postamble
0.40
0.60
0.40
0.60
tCK
tWPRE
Write preamble
0.35
-
0.35
-
tCK
tIH
Address and control input hold time
275
-
250
-
ps
tIS
Address and control input setup time
200
-
175
-
ps
tRPRE
Read preamble
0.90
1.10
0.90
1.10
tCK
tRPST
Read postamble
0.40
0.60
0.40
0.60
tCK
tRRD
Active bank A to Active bank B command
7.5
-
7.5
-
ns
tDelay
Minimum time clocks remains ON after CKE
asynchronously drops Low
tIS + tCK
+ tIH
-
tIS + tCK
+ tIH
-
ns
tREFI
Average Periodic Refresh Interval
(85ºC < T
CASE
≤ 95ºC)
3.9
3.9
μs
Average Periodic Refresh Interval
(0ºC ≤ T
CASE
≤ 85ºC)
7.8
7.8
μs
tOIT
OCD drive mode output delay
0
12
0
12
ns
tCCD
 to 
2
2
tCK