Datasheet

M2Y51H64TU88D0B / M2Y51H64TU88D6B / M2Y1GH64TU8HD0B / M2Y1GH64TU8HD6B
512MB: 64M x 64 / 1GB: 128M x 64
Unbuffered DDR2 SDRAM DIMM Preliminary Edition
REV 0.1 12
08/2008
© NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Operating, Standby, and Refresh Currents
T
CASE
= 0 °C ~ 85 °C; V
DDQ
= V
DD
= 1.8V ± 0.1V (512MB, 1 Rank, 64Mx8 DDR2 SDRAMs)
Symbol
Parameter/Condition
PC2-5300
PC2-6400
Unit
I DD0
Operating Current: one bank; active/precharge; tRC = tRC (MIN);
tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per
clock cycle; address and control inputs changing once per clock
cycle
TBD
TBD
mA
I DD1
Operating Current: one bank; active/read/precharge; Burst = 2;
tRC = tRC (MIN); CL=2.5; tCK = tCK (MIN); IOUT = 0mA; address and
control inputs changing once per clock cycle
TBD
TBD
mA
I DD2P
Precharge Power-Down Standby Current: all banks idle;
power-down mode; CKE  VIL (MAX); tCK = tCK (MIN)
TBD
TBD
mA
I DD2N
Idle Standby Current: CS  VIH (MIN); all banks idle; CKE  VIH
(MIN); tCK = tCK (MIN); address and control inputs changing once
per clock cycle
TBD
TBD
mA
I DD2Q
Precharge Quiet Standby Current: All banks idle;  is HIGH;
CKE is HIGH; t
CK
= t
CK (MIN)
; Other control and address inputs are
stable, Data bus inputs are floating.
TBD
TBD
mA
I DD3PF
Active Power-Down Current: All banks open; tCK = tCK (MIN),
CKE is LOW; Other control and address inputs are STABLE,
Data bus inputs are floating. MRS A12 bit is set to low (Fast
Power-down Exit).
TBD
TBD
mA
I DD3PS
Active Power-Down Current: All banks open; tCK = tCK (MIN),
CKE is LOW; Other control and address inputs are STABLE,
Data bus inputs are floating. MRS A12 bit is set to high (Slow
Power-down Exit).
TBD
TBD
mA
I DD3N
Active Standby Current: one bank; active/precharge; CS  VIH
(MIN); CKE  VIH (MIN); tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM,
and DQS inputs changing twice per clock cycle; address and
control inputs changing once per clock cycle
TBD
TBD
mA
I DD4W
Operating Current: one bank; Burst = 2; writes; continuous burst;
address and control inputs changing once per clock cycle; DQ
and DQS inputs changing twice per clock cycle; CL=2.5; tCK =
tCK (MIN)
TBD
TBD
mA
I DD4R
Operating Current: one bank; Burst = 2; reads; continuous burst;
address and control inputs changing once per clock cycle; DQ
and DQS outputs changing twice per clock cycle; CL = 2.5; tCK =
tCK (MIN); IOUT = 0mA
TBD
TBD
mA
I DD5
Auto-Refresh Current: tRC = tRFC (MIN)
TBD
TBD
mA
I DD6
Self-Refresh Current: CKE  0.2V
TBD
TBD
mA
I DD7
Operating Current: four bank; four bank interleaving with BL = 4,
address and control inputs randomly changing; 50% of data
changing at every transfer; tRC = tRC (min); IOUT = 0mA.
TBD
TBD
mA