Datasheet

M2U51264DS8HB3G / M2U25664DS88B3G / M2U12864DSH4B3G
512MB, 256MB and 128MB
PC3200, PC2700 and PC2100
Unbuffered DDR DIMM
REV 2.2 8
Aug 3, 2004
Preliminary
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Serial Presence Detect
SPD Description
Byte Description Byte Description
0 Number of Serial PD Bytes Written during Production 26 Maximum Data Access Time from Clock at CL=1
1 Total Number of Bytes in Serial PD device 27 Minimum Row Precharge Time (t
RP
)
2 Fundamental Memory Type 28 Minimum Row Active to Row Active delay (t
RRD
)
3 Number of Row Addresses on Assembly 29 Minimum RAS to CAS delay (t
RCD
)
4 Number of Column Addresses on Assembly 30 Minimum RAS Pulse Width (t
RAS
)
5 Number of DIMM Rank 31 Module Bank Density
6 Data Width of Assembly 32 Address and Command Setup Time Before Clock
7 Data Width of Assembly (cont’) 33 Address and Command Hold Time After Clock
8 Voltage Interface Level of this Assembly 34 Data Input Setup Time Before Clock
9
DDR SDRAM Device Cycle Time
CL=2.5
35 Data Input Hold Time After Clock
10
DDR SDRAM Device Access Time from Clock
CL=2.5
36-40 Reserved
11 DIMM Configuration Type 41 Minimum Active/Auto-refresh Time (t
RC
)
12 Refresh Rate/Type 42
Auto-refresh to Active/Auto-refresh Command Period
(t
RFC
)
13 Primary DDR SDRAM Width 43 Max Cycle Time (t
CK max
)
14 Error Checking DDR SDRAM Device Width 44 Maximum DQS-DQ Skew Time (t
DQSQ
)
15
DDR SDRAM Device Attr: Min CLK Delay, Random Col
Access
45 Maximum Read Data Hold Skew Factor (t
QHS
)
16
DDR SDRAM Device Attributes: Burst Length
Supported
46-61 Reserved
17
DDR SDRAM Device Attributes: Number of Device
Banks
62 SPD Revision
18
DDR SDRAM Device Attributes:
CAS Latencies Supported
63 Checksum Data
19 DDR SDRAM Device Attributes: CS Latency 64-71 Manufacturer’s JEDEC ID Code
20 DDR SDRAM Device Attributes: WE Latency 72 Module Manufacturing Location
21 DDR SDRAM Device Attributes: 73-90 Module Part number
22 DDR SDRAM Device Attributes: General 91-92 Module Revision Code
23
Minimum Clock Cycle
CL=2.5
93-94
Module Manufacturing Data
yy= Binary coded decimal year code, 0-99(Decimal),
00-63(Hex)
ww= Binary coded decimal year code, 01-52(Decimal),
01-34(Hex)
24
Maximum Data Access Time from Clock at
CL=2
95-98 Module Serial Number
25 Minimum Clock Cycle Time at CL=1 99-127 Reserved