Datasheet

M2S4G64CB88B5N / M2S8G64CB8HB5N
4GB: 512M x 64 / 8GB: 1024M x 64
PC3-10600 / PC3-12800
Unbuffered DDR3 SO-DIMM
REV 1.0 12
06/2012
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
AC Timing Specifications for DDR3 SDRAM Devices Used on Module (1066MHz)
Parameter
Symbol
DDR3-1066
Units
Notes
Min.
Max.
Clock Timing
Minimum Clock Cycle Time (DLL off mode)
tCK (DLL_OFF)
8
-
ns
Average Clock Period
tCK(avg)
Refer to "Standard Speed Bins)
ps
Average high pulse width
tCH(avg)
0.47
0.53
tCK(avg)
Average low pulse width
tCL(avg)
0.47
0.53
tCK(avg)
Absolute Clock Period
tCK(abs)
Min.: tCK(avg)min + tJIT(per)min
Max.: tCK(avg)max + tJIT(per)max
ps
Absolute clock HIGH pulse width
tCH(abs)
0.43
-
tCK(avg)
Absolute clock LOW pulse width
tCL(abs)
0.43
-
tCK(avg)
Clock Period Jitter
JIT(per)
-90
90
ps
Clock Period Jitter during DLL locking period
JIT(per, lck)
-80
80
ps
Cycle to Cycle Period Jitter
tJIT(cc)
180
180
ps
Cycle to Cycle Period Jitter during DLL locking period
JIT(cc, lck)
160
160
ps
Duty Cycle Jitter
tJIT(duty)
-
-
ps
Cumulative error across 2 cycles
tERR(2per)
-132
132
ps
Cumulative error across 3 cycles
tERR(3per)
-157
157
ps
Cumulative error across 4 cycles
tERR(4per)
-175
175
ps
Cumulative error across 5 cycles
tERR(5per)
-188
188
ps
Cumulative error across 6 cycles
tERR(6per)
-200
200
ps
Cumulative error across 7 cycles
tERR(7per)
-209
209
ps
Cumulative error across 8 cycles
tERR(8per)
-217
217
ps
Cumulative error across 9 cycles
tERR(9per)
-224
224
ps
Cumulative error across 10 cycles
tERR(10per)
-231
231
ps
Cumulative error across 11 cycles
tERR(11per)
-237
237
ps
Cumulative error across 12 cycles
tERR(12per)
-242
242
ps
Cumulative error across n = 13, 14 . . . 49, 50 cycles
tERR(nper)
tERR(nper)min = (1 + 0.68ln(n)) * tJIT(per)min
tERR(nper)max = (1 + 0.68ln(n)) * tJIT(per)max
ps
Data Timing
DQS, DQS# to DQ skew, per group, per access
tDQSQ
-
150
ps
DQ output hold time from DQS, DQS#
tQH
0.38
-
tCK(avg)
DQ low-impedance time from CK, CK#
tLZ(DQ)
-600
300
ps
DQ high impedance time from CK, CK#
tHZ(DQ)
-
300
ps
Data setup time to DQS, DQS# referenced to Vih(ac) / Vil(ac) levels
tDS(base)
AC175
25
ps
Data setup time to DQS, DQS# referenced to Vih(ac) / Vil(ac) levels
tDS(base)
AC150
75
ps
Data hold time from DQS, DQS# referenced to Vih(dc) / Vil(dc) levels
tDH(base)
DC100
100
ps
DQ and DM Input pulse width for each input
tDIPW
490
ps
Data Strobe Timing
DQS,DQS# differential READ Preamble
tRPRE
0.9
Note 19
tCK(avg)
DQS, DQS# differential READ Postamble
tRPST
0.3
Note 11
tCK(avg)
DQS, DQS# differential output high time
tQSH
0.38
-
tCK(avg)
DQS, DQS# differential output low time
tQSL
0.38
-
tCK(avg)
DQS, DQS# differential WRITE Preamble
tWPRE
0.9
-
tCK(avg)
DQS, DQS# differential WRITE Postamble
tWPST
0.3
-
tCK(avg)
DQS, DQS# rising edge output access time from rising CK, CK#
tDQSCK
-300
300
tCK(avg)
DQS and DQS# low-impedance time
(Referenced from RL - 1)
tLZ(DQS)
-600
300
tCK(avg)
DQS and DQS# high-impedance time
(Referenced from RL + BL/2)
tHZ(DQS)
-
300
tCK(avg)
DQS, DQS# differential input low pulse width
tDQSL
0.45
0.55
tCK(avg)
DQS, DQS# differential input high pulse width
tDQSH
0.45
0.55
tCK(avg)
DQS, DQS# rising edge to CK, CK# rising edge
tDQSS
-0.25
0.25
tCK(avg)
DQS, DQS# falling edge setup time to CK, CK# rising edge
tDSS
0.2
-
tCK(avg)
DQS, DQS# falling edge hold time from CK, CK# rising edge
tDSH
0.2
-
tCK(avg)