Datasheet

M2S2G64CB(C)88G5N / M2S4G64CB(C)8HG5N
2GB: 256M x 64 / 4GB: 512M x 64
PC3(L)-10600 / PC3(L)-12800
Unbuffered DDR3(L) SO-DIMM
REV 1.0 15
05/2011
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Timing of RD/RDA command to Power Down entry
Trdpden
tRDPDENmin.: RL+4+1
tRDPDENmax.: -
Nck
Timing of WR command to Power Down entry
(BL8OTF, BL8MRS, BC4OTF)
Twrpden
tWRPDENmin.: WL + 4 + (Twr / Tck(avg))
tWRPDENmax.: -
Nck
Timing of WRA command to Power Down entry
(BL8OTF, BL8MRS, BC4OTF)
Twrapden
tWRAPDENmin.: WL+4+WR+1
tWRAPDENmax.: -
Nck
Timing of WR command to Power Down entry (BC4MRS)
Twrpden
tWRPDENmin.: WL + 2 + (Twr / Tck(avg))tWRPDENmax.: -
Nck
Timing of WRA command to Power Down entry
(BC4MRS)
Twrapden
tWRAPDENmin.: WL + 2 +WR + 1
tWRAPDENmax.: -
Nck
Timing of REF command to Power Down entry
Trefpden
tREFPDENmin.: 1
tREFPDENmax.: -
Nck
Timing of MRS command to Power Down entry
Tmrspden
tMRSPDENmin.: Tmod(min)
tMRSPDENmax.: -
ODT Timings
ODT high time without write command or
with write command and BC4
ODTH4
ODTH4min.: 4
ODTH4max.: -
Nck
ODT high time with Write command and BL8
ODTH8
ODTH8min.: 6
ODTH8max.: -
Nck
Asynchronous RTT turn-on delay
(Power-Down with DLL frozen)
Taonpd
2
8.5
ns
Asynchronous RTT turn-off delay
(Power-Down with DLL frozen)
Taofpd
2
8.5
ns
RTT turn-on
Taon
-300
300
ps
RTT_Nom and RTT_WR turn-off time
from ODTLoff reference
Taof
0.3
0.7
Tck(avg)
RTT dynamic change skew
Tadc
0.3
0.7
Tck(avg)
Write Leveling Timings
First DQS/DQS# rising edge after
write leveling mode is programmed
Twlmrd
40
-
Nck
DQS/DQS# delay after write leveling mode is programmed
Twldqsen
25
-
Nck
Write leveling setup time from rising CK, CK#
crossing to rising DQS, DQS# crossing
Twls
245
-
ps
Write leveling hold time from rising DQS, DQS#
crossing to rising CK, CK# crossing
Twlh
245
-
ps
Write leveling output delay
Twlo
0
9
ns
Write leveling output error
Twloe
0
2
ns