Datasheet

M2S2G64CB(C)88G5N / M2S4G64CB(C)8HG5N
2GB: 256M x 64 / 4GB: 512M x 64
PC3(L)-10600 / PC3(L)-12800
Unbuffered DDR3(L) SO-DIMM
REV 1.0 14
05/2011
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Command and Address Timing
DLL locking time
Tdllk
512
-
Nck
Internal READ Command to PRECHARGE Command delay
Trtp
tRTPmin.: max(4Nck, 7.5ns)
tRTPmax.: -
Delay from start of internal write
transaction to internal read command
Twtr
tWTRmin.: max(4Nck, 7.5ns)
tWTRmax.:
WRITE recovery time
Twr
15
-
ns
Mode Register Set command cycle time
Tmrd
4
-
Nck
Mode Register Set command update delay
Tmod
tMODmin.: max(12Nck, 15ns)
tMODmax.:
ACT to internal read or write delay time
Trcd
PRE command period
Trp
ACT to ACT or REF command period
Trc
CAS# to CAS# command delay
Tccd
4
-
Nck
Auto precharge write recovery + precharge time
Tdal(min)
WR + roundup(Trp / Tck(avg))
Nck
Multi-Purpose Register Recovery Time
Tmprr
1
-
Nck
ACTIVE to PRECHARGE command period
Tras
Standard Speed Bins
ACTIVE to ACTIVE command period for 1KB page size
Trrd
max(4Nck, 7.5ns)
-
ACTIVE to ACTIVE command period for 2KB page size
Trrd
tRRDmin.: max(4Nck, 10ns)
tRRDmax.:
Four activate window for 1KB page size
Tfaw
37.5
-
ns
Four activate window for 2KB page size
Tfaw
50
-
ns
Command and Address setup time to CK, CK#
referenced to Vih(ac) / Vil(ac) levels
Tis(base)
125
-
ps
Command and Address hold time from CK, CK#
referenced to Vih(dc) / Vil(dc) levels
Tih(base)
200
-
ps
Command and Address setup time to CK, CK#
referenced to Vih(ac) / Vil(ac) levels
Tis(base)
AC150
125+150
-
ps
Control and Address Input pulse width for each input
Tipw
780
-
ps
Calibration Timing
Power-up and RESET calibration time
tZQinit
512
-
Nck
Normal operation Full calibration time
tZQoper
256
-
Nck
Normal operation Short calibration time
Tzqcs
64
-
Nck
Reset Timing
Exit Reset from CKE HIGH to a valid command
Txpr
tXPRmin.: max(5Nck, Trfc(min) + 10ns)
tXPRmax.: -
Self Refresh Timings
Exit Self Refresh to commands not requiring a locked DLL
Txs
tXSmin.: max(5Nck, Trfc(min) + 10ns)
tXSmax.: -
Exit Self Refresh to commands requiring a locked DLL
Txsdll
tXSDLLmin.: Tdllk(min)
tXSDLLmax.: -
Nck
Minimum CKE low width for Self Refresh entry to exit timing
Tckesr
tCKESRmin.: Tcke(min) + 1 Nck
tCKESRmax.: -
Valid Clock Requirement after Self Refresh Entry (SRE)
or Power-Down Entry (PDE)
Tcksre
tCKSREmin.: max(5 Nck, 10 ns)
tCKSREmax.: -
Valid Clock Requirement before Self Refresh Exit (SRX)
or Power-Down Exit (PDX) or Reset Exit
Tcksrx
tCKSRXmin.: max(5 Nck, 10 ns)
tCKSRXmax.: -
Power Down Timings
Exit Power Down with DLL on to any valid command;
Exit Precharge Power Down with DLL frozen to commands
not requiring a locked DLL
Txp
tXPmin.: max(3Nck, 7.5ns)
tXPmax.: -
Exit Precharge Power Down with DLL frozen to commands
requiring a locked DLL
Txpdll
tXPDLLmin.: max(10Nck, 24ns)
tXPDLLmax.: -
CKE minimum pulse width
Tcke
tCKEmin.: max(3Nck 5.625ns)
tCKEmax.: -
Command pass disable delay
Tcpded
tCPDEDmin.: 1
tCPDEDmin.: -
Nck
Power Down Entry to Exit Timing
Tpd
tPDmin.: Tcke(min)
tPDmax.: 9*Trefi
Timing of ACT command to Power Down entry
Tactpden
tACTPDENmin.: 1
tACTPDENmax.: -
Nck
Timing of PRE or PREA command to Power Down entry
Tprpden
tPRPDENmin.: 1
tPRPDENmax.: -
Nck