Datasheet

M2Y(F)1G64TU88G7(4) B / M2Y(F)2G64TU8HG5(4) B
1GB: 128M x 64 / 2GB: 256M x 64
Unbuffered DDR2 SDRAM DIMM
REV 1.0 7
10/2010
© NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Serial Presence Detect (1GB – 1 Rank, DDR2 SDRAMs)
Serial Presence Detect [1GB –1 Rank, DDR2 SDRAMs]
Byte
Description
SPD Data Entry (Hex.)
-AC
0
Number of Serial PD Bytes Written during Production
80
1
Total Number of Bytes in Serial PD device
08
2
Fundamental Memory Type
08
3
Number of Row Addresses on Assembly
0E
4
Number of Column Addresses on Assembly
0A
5
Number of DIMM Ranks, Package, and Height
60
6
Data Width of Assembly
40
7
Reserved
00
8
Voltage Interface Level of this Assembly
05
9
DDR2 SDRAM Device Cycle Time at CL=5
25
10
DDR2 SDRAM Device Access Time (t
ac
) from Clock at CL=5
40
11
DIMM Configuration Type
00
12
Refresh Rate/Type
82
13
Primary DDR2 SDRAM Width
08
14
Error Checking DDR2 SDRAM Device Width
00
15
Reserved
00
16
DDR2 SDRAM Device Attributes: Burst Length Supported
0C
17
DDR2 SDRAM Device Attributes: Number of Device Banks
08
18
DDR2 SDRAM Device Attributes:  Latencies Supported
38
19
DIMM Mechanical Characteristics
01
20
DDR2 SDRAM DIMM Type Information
02
21
DDR2 SDRAM Module Attributes
00
22
DDR2 SDRAM Device Attributes: General
03
23
Minimum Clock Cycle at CL=4
3D
24
Maximum Data Access Time from Clock at CL=4
50
25
Minimum Clock Cycle Time at CL=3
50
26
Maximum Data Access Time from Clock at CL=3
60
27
Minimum Row Precharge Time (t
RP
)
32
28
Minimum Row Active to Row Active delay (t
RRD
)
1E
29
Minimum  to  delay (t
RCD
)
32
30
Minimum Active to Precharge Time (t
RAS
)
2D
31
Module Rank Density
01
32
Address and Command Setup Time Before Clock (t
IS
)
17
33
Address and Command Hold Time After Clock (t
IH
)
25
34
Data Input Setup Time Before Clock (t
DS
)
05
35
Data Input Hold Time After Clock (tDH)
12
36
Write Recovery Time (t
WR
)
3C
37
Internal Write to Read Command delay (t
WTR
)
1E
38
Internal Read to Precharge delay (t
RTP
)
1E
39
Reserved
00
40
Extension of Byte 41 t
RC
and Byte 42 t
RFC
36
41
Minimum Core Cycle Time (t
RC
)
39
42
Min. Auto Refresh Command Cycle Time (t
RFC
)
7F
43
Maximum Clock Cycle Time (t
CK
)
80
44
Max. DQS-DQ Skew Factor (tQHS)
14
45
Read Data Hold Skew Factor (tQHS)
1E
46-61
Reserved
--
62
SPD Reversion
13
63
Checksum for Byte 0-62
F9
64-71
Manufacturer’s JEDEC ID Code
--
72
Module Manufacturing Location
00
73-91
Module Part number
--
92-255
Reserved
--