Datasheet

M2Y(F)1G64TU88G7(4) B / M2Y(F)2G64TU8HG5(4) B
1GB: 128M x 64 / 2GB: 256M x 64
Unbuffered DDR2 SDRAM DIMM
REV 1.0 11
10/2010
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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Operating, Standby, and Refresh Currents
T
CASE
= 0 °C ~ 85 °C; V
DDQ
= V
DD
= 1.8V ± 0.1V (2GB, 2 Ranks, 128Mx8 DDR2 SDRAMs)
Symbol
Parameter/Condition
PC2-6400
Unit
I DD0
Operating Current: one bank; active/precharge; Trc = Trc (MIN); Tck = Tck
(MIN); DQ, DM, and DQS inputs changing twice per clock cycle; address
and control inputs changing once per clock cycle
968
mA
I DD1
Operating Current: one bank; active/read/precharge; Burst = 2; Trc = Trc
(MIN); CL=2.5; Tck = Tck (MIN); IOUT = 0Ma; address and control inputs
changing once per clock cycle
1100
mA
I DD2P
Precharge Power-Down Standby Current: all banks idle; power-down
mode; CKE  VIL (MAX); Tck = Tck (MIN)
158
mA
I DD2N
Idle Standby Current: CS  VIH (MIN); all banks idle; CKE  VIH (MIN); Tck
= Tck (MIN); address and control inputs changing once per clock cycle
704
mA
I DD2Q
Precharge Quiet Standby Current: All banks idle;  is HIGH; CKE is
HIGH; t
CK
= t
CK (MIN)
; Other control and address inputs are stable, Data
bus inputs are floating.
616
mA
I DD3PF
Active Power-Down Current: All banks open; Tck = Tck (MIN), CKE is
LOW; Other control and address inputs are STABLE, Data bus inputs
are floating. MRS A12 bit is set to low (Fast Power-down Exit).
528
mA
I DD3PS
Active Power-Down Current: All banks open; Tck = Tck (MIN), CKE is
LOW; Other control and address inputs are STABLE, Data bus inputs
are floating. MRS A12 bit is set to high (Slow Power-down Exit).
176
mA
I DD3N
Active Standby Current: one bank; active/precharge; CS  VIH (MIN);
CKE  VIH (MIN); Trc = Tras (MAX); Tck = Tck (MIN); DQ, DM, and DQS
inputs changing twice per clock cycle; address and control inputs
changing once per clock cycle
792
mA
I DD4W
Operating Current: one bank; Burst = 2; writes; continuous burst;
address and control inputs changing once per clock cycle; DQ and DQS
inputs changing twice per clock cycle; CL=2.5; Tck = Tck (MIN)
1408
mA
I DD4R
Operating Current: one bank; Burst = 2; reads; continuous burst;
address and control inputs changing once per clock cycle; DQ and DQS
outputs changing twice per clock cycle; CL = 2.5; Tck = Tck (MIN); IOUT =
0Ma
1408
mA
I DD5
Auto-Refresh Current: Trc = Trfc (MIN)
1892
mA
I DD6
Self-Refresh Current: CKE  0.2V
158
mA
I DD7
Operating Current: four bank; four bank interleaving with BL = 4,
address and control inputs randomly changing; 50% of data changing at
every transfer; Trc = Trc (min); IOUT = 0Ma.
2552
mA
Note: Module IDD was calculated from component IDD. It may differ from the actual measurement.