Datasheet

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ELECTRONIC ASSEMBLY reserves the right to change specifications without prior notice.
EA DOGM204-A
SERIAL INTERFACE (SPI)
The serial interface always needs a synchronization byte. In write mode, the byte to send hast to be
devided in two bytes, into the “lower data“ and “upper data“. Please refer to the chart below. The
maximum clock frequency for SCLK is 1 MHz.
SPI, 2-/3-WIRE
With 2 or 3 lines SCLK, SID and SOD (if necessary) the display EA DOGM204-A may be connected
directly to the SPI interface of a µC.
SPI, 4-WIRE
If there is more than one component connected to the SPI, an additional „Chipselect“ line is required.
For those you need to insert an AND-gate (e.g. 74HC1G08) with the SCLK line. On page 4 you do
find an application example. Please mention that the logic for CS ist H-active.
I²C INTERFACE
The display can be assigned to the slave adress 0x78 or 0x7A (PIN SA0). After transfering the start
condition, the hardware adress, togehter with the Read(1)/Write(0) bit has to be transmitted. While
writing to the display, after the slave adress, there always is a control byte holding the information
Data(1) or Command(0) and the continuation bit. If the continuation bit is set to 0, the following bytes
are data bytes until the next stop condition occurs. The maximum clock rate for I²C bus is 400 kHz.
Further information about the interfaces and the timing of the SSD1803A, please refer to the datasheet
http://www.lcd-module.de/fileadmin/eng/pdf/zubehoer/ssd1803a_2_0.pdf