Datasheet

EA eDIPTFT70-A
Page 6
ELECTRONIC ASSEMBLY reserves
the right to change specifications
without prior notice. Printing and
typographical errors reserved.
SPI INTERFACE
If the display is wired as
shown below, SPI mode is
activated.
The data is then transferred
via the serial, synchronous
SPI interface.
The transfer parameter will be
set via the pins DORD, CPOL
and CPHA.
Note:
The pins DORD, CPOL, CPHA,
DPOM, DPROT and TEST/SBUF
have an internal pullup, which is
why only the LO level
(0=GND) is to be actively applied.
These pins must be left open for a Hi
level.
On pin 20 (SBUF) the display indicates with a low level that data is ready to be retrieved from the internal send buffer.
The line can be connected to an interrupt input of the host system, for example.
DATA TRANSFER SPI
Write operation: a clock rate up to 200 kHz is allowed
without any stop. Together with a pause of 100 µs
between every data byte a clock rate up to 3 MHz can
be reached.
Read operation: to read data (e.g. the „ACK“ byte) a
dummy byte (e.g . 0xFF) need to be sent.
Note that the EA eDIP for internal operation does need
a short time before providing the data; therefore a short
pause of min. 6µs (no activity of CLK line) is needed for
each byte.
application example
Pinout eDIPTFT70-A: SPI mode
Pin Symbol In/Out Function Pin Symbol In/Out Function
1GND Ground Potential for logic (0V) 25
N.C. do not connect, reserved
2VDD Power supply for logic (+5V) 26
3 SND+ Speaker LS1 (Impedance 8 Ohm) 27
4 SND- Speaker LS2 28
5 RESET In L: Reset 29 GND Ground (=Pin 1)
6 SS In Slave Select 30 VDD Power supply (=Pin 2)
7 MOSI In Serial In 31 AIN1
In
analogue input 0..VDD
DC impedance 1MOhm
8 MISO Out Serial Out 32 AIN2
9 CLK In Shift Clock 33 OUT1 / MO8
Out
8 digital outputs
maximum current:
IOL = IOH = 10mA
alternativ up to 8 matrix
keyboard output lines
(reduces the digital output
lines, see chapter external
keyboard)
10 DORD In Data Order (0=MSB first; 1=LSB first) 34 OUT2 / MO7
11 SPIMOD In connect to GND for SPI interface 35 OUT3 / MO6
12 NC do not connect 36 OUT4 / MO5
13 DPOM In
L: disable PowerOnMacro
do not connect for normal operation
37 OUT5 / MO4
14 CPOL In Clock Polarity (0=LO 1=HI when idle) 38 OUT6 / MO3
15 CPHA In Clock Phase sample 0=1st;1=2nd edge 39 OUT7 / MO2
16 BUZZ Out Buzzer output 40 OUT8 / MO1
17 DPROT In
L: Disable Smallprotokoll
do not connect for normal operation
41 IN1 / MI8
In
8 digital inputs
open-drain with internal
pullup 20..50k
alternativ up to 8 matrix
keyboard input lines
(reduces the digital input
lines, see chapter external
keyboard)
18 DNC Out L: internal, do not connect 42 IN2 / MI7
19 WP In L: Writeprotect for DataFlash 43 IN3 / MI6
20
TEST
SBUF
IN
Out
open-drain with internal pullup 20..50k
IN (Power-On) L: Testmode
OUT L: data in sendbuffer
44 IN4 / MI5
21
N.C. do not connect, reserved
45 IN5 / MI4
22 46 IN6 / MI3
23 47 IN7 / MI2
24 48 IN8 / MI1