User`s manual

7
DSP “Processing Engine” I/O Interconnect
The ISP-100’s processing engine is comprised of three Motorola 56004 DSP
chips. There is a specific input/output interconnect between these chips that
needs to be understood before working with the QuickBUILD

software. Here is
a diagram of the DSP interconnects:
(*Slot 2 Can Be Input and/or Output)
Figure 2.
As you can see from the diagram, DSP 1 is responsible for accepting input
signals from slots 1 and 2, inputs 1a, 1b, 2a, and 2b.
DSP 2 is responsible for output on slots 2 and 3, output 2a, 2b, 3a, and 3b.
DSP 3 is responsible for output on slots 4 and 5, output 4a, 4b, 5a, and 5b.
The interconnects between DSP chips are labeled by TX and RX designators.
The “T” in TX stands for “Transmit” and the “R” in RX stands for Receive. Each
Motorola 56004 is capable of four inputs, or receive channels, and six outputs, or
transmit channels. They are labeled as follows:
INPUTS: OUTPUTS:
RX0L TX0L
RX0R TX0R
RX1L TX1L
RX1R TX1R
TX2L
TX2R
To simplify the diagram, only the TX designators for DSP 1 and one pair of TX
designators for DSP 2 have been labeled.


