Data Sheet

iEthernet W5200

cleared by writing IR(Interrupt Register) or Sn_IR (Socket

n-th Interrupt Register). All interrupts are maskable. This

pin is active low.

SCLK I 42 SPI CLOCK

This pin is used to SPI Clock signal Pin when using SPI

interface.

MOSI I 43 SPI MASTER OUT SLAVE IN

This pin is used to SPI MOSI signal pin when using SPI

interface.

MISO O 44 SPI MASTER IN SLAVE OUT

This pin is used to SPI MISO signal pin.

PWDN I 45 POWER DOWN ( Active HIGH )

This pin is used to power down pin.

Low : Normal Mode Enable

High : Power Down Mode Enable

1.2 PHY Signals

Symbol Type Pin No Description

RXIP

I 20 RXIP/RXIN Signal Pair

The differential data from the media is received on

the RXIP/RXIN signal pair.

RXIN

I 21

TXOP O 17 TXOP/TXON Signal Pair

The differential data is transmitted to the media on

the TXOP/TXIN signal pair.

TXON O 18

BIAS O 12 BIAS Register

Connect a resistor of 28.7㏀±1% to the ground.

Refer to the “Reference schematic”.

ANE I 29 Auto Negotiation Mode Enable

This pin selects Enable/Disable of Auto Negotiation

Mode.

Low :Auto Negotiation Mode Disable

High : Auto Negotiation Mode Enable

DUP I 30 Full Duplex Mode Enable

This pin selects Enable/Disable of Full Duplex Mode.

Low = Half Duplex Mode Enable

High = Full Duplex Mode Enable

This function activates only during reset period.

SPD I 31 Speed Mode