Data Sheet

© Copyright 2012 WIZnet Co., Inc. All rights reserved.
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iEthernet W5200
Figure 8 Allocation Internal TX/RX memory of Socket n-th
Sn_TXMEM_SIZE(ch) = 2K,
Chip base address = 0x0000
Socket 7
Socket 6
Socket 5
Socket 4
Socket 3
Socket 2
Socket 1
Socket 0
gS0_TX_BASE = 0x8000
gS0_TX_MASK = 0x07FF
0x8000
0x8800
0x9000
0x9800
0xA000
0xA800
0xB000
0xB800
0xC000
gS1_TX_BASE = 0x8800
gS1_TX_MASK = 0x07FF
gS2_TX_BASE = 0x9000
gS2_TX_MASK = 0x07FF
gS3_TX_BASE = 0x9800
gS3_TX_MASK = 0x07FF
gS4_TX_BASE = 0xA000
gS4_TX_MASK = 0x07FF
gS5_TX_BASE = 0xA800
gS5_TX_MASK = 0x07FF
gS6_TX_BASE = 0xB000
gS6_TX_MASK = 0x07FF
gS7_TX_BASE = 0xB800
gS7_TX_MASK = 0x07FF
Sn_RXMEM_SIZE(ch) = 2K,
Chip base address = 0x0000
Socket 7
Socket 6
Socket 5
Socket 4
Socket 3
Socket 2
Socket 1
Socket 0
gS0_RX_BASE = 0xC000
gS0_RX_MASK = 0x07FF
0xC000
0xC800
0xD000
0xD800
0xE000
0xE800
0xF000
0xF800
gS1_RX_BASE = 0xC800
gS1_RX_MASK = 0x07FF
gS2_RX_BASE = 0xD000
gS2_RX_MASK = 0x07FF
gS3_RX_BASE = 0xD800
gS3_RX_MASK = 0x07FF
gS4_RX_BASE = 0xE000
gS4_RX_MASK = 0x07FF
gS5_RX_BASE = 0xE800
gS5_RX_MASK = 0x07FF
gS6_RX_BASE = 0xF000
gS6_RX_MASK = 0x07FF
gS7_RX_BASE = 0xF800
gS7_RX_MASK = 0x07FF
(a) TX memory
(b) RX memory