Data Sheet

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22
iEthernet W5200
PHYSTATUS(W5200 PHY status Register)[R/W][0x0035][0x00]
PHYSTATUS is the Register to indicate W5200 status of PHY.
Bit Symbol Description
7 Reserved Reserved
6 Reserved Reserved
5 LINK
Link Status Register[Read Only]
This register indicates Link status.
0 : Link down
1 : Link Up
4 Reserved Reserved
3 POWERDOWN
Power down mode of PHY[Read Only]
This register indicates status of Power down mode
0 : Disable Power down mode(operates normal mode)
1 : Enable Power down mode
2 Reserved Reserved
1 Reserved Reserved
0 Reserved Reserved
IMR2(Interrupt Mask Register2)[R/W][0x0016][0x00]
The Interrupt Mask Register is used to mask interrupts. Each interrupt mask bit corresponds to
a bit in the Interrupt Register2 (IR2). If an interrupt mask bit is set, an interruption will be
issued whenever the corresponding bit in the IR2 is set. If any bit in the IMR is set as ‘0’ an
interrupt will not occur though the bit.
7 6 5 4 3 2 1 0
S7_INT S6_INT S5_INT
S4_INT S3_INT S2_INT S1_INT S0_INT
Bit Symbol Description
7 S7_INT IR(S7_INT) Interrupt Mask
6 S6_INT IR(S6_INT) Interrupt Mask
5 S5_INT IR(S5_INT) Interrupt Mask
4 S4_INT IR(S4_INT) Interrupt Mask
3 S3_INT IR(S3_INT) Interrupt Mask
2 S2_INT IR(S2_INT) Interrupt Mask
1 S1_INT IR(S1_INT) Interrupt Mask
0 S0_INT IR(S0_INT) Interrupt Mask