Data Sheet

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21
iEthernet W5200
IR2(W5200 SOCKET Interrupt Register)[R/W][0x0034][0x00]
IR2 is the Register to notify W5200 SOCKET interrupt to the Host. If any interrupt occurs, the
related bit of IR2 is set as ‘1’. When related Mask Bit is ‘1’, nINT signal is asserted low. nINT
keeps low until all bits of Sn_IR becomes ‘0’. If all bits of Sn_IR become ‘0’, it becomes high
automatically.
7 6 5 4 3 2 1 0
S7_INT
S6_INT
S5_INT
S4_INT S3_INT S2_INT S1_INT S0_INT
Bit Symbol Description
7 S7_INT
When an interrupt occurs at SOCKET 7-th
, it becomes ‘1’. This
interrupt information is applied to S7_IR
. This bit is automatically
cleared when S7_IR is cleared to 0x00 by host.
6 S6_INT
When an interrupt occurs at SOCKET 6-th
, it becomes ‘1’. This
interrupt information is applied to S6_IR. This bit is automatically
cleared when S6_IR is cleared to 0x00 by host.
5 S5_INT
When an interrupt occurs at SOCKET 5-th, it becomes ‘1’. This
interrupt information is applied to S5_IR. This bit is automatically
cleared when S5_IR is cleared to 0x00 by host.
4 S4_INT
When an interrupt occurs at SOCKET 4-th
, it becomes ‘1’. This
interrupt information is applied to S4_IR. This bit is automatically
cleared when S4_IR is cleared to 0x00 by host.
3 S3_INT
When an interrupt occurs at SOCKET 3-th
, it becomes ‘1’. This
interrupt information is applied to S3_IR. This bit is automatically
cleared when S3_IR is cleared to 0x00 by host.
2 S2_INT
When an interrupt occurs at SOCKET 2-th
, it becomes ‘1’. This
interrupt information is applied to S2_IR. This bit is automatically
cleared when S2_IR is cleared to 0x00 by host.
1 S1_INT
When an interrupt occurs at SOCKET 1-th
, it becomes ‘1’. This
interrupt information is applied to S1_IR. This bit is automatically
cleared when S1_IR is cleared to 0x00 by host.
0 S0_INT
When an interrupt occurs at SOCKET 0-th
, it becomes ‘0’. This
interrupt information is applied to S0_IR. This bit is automatically
cleared when S0_IR is cleared to 0x00 by host.