Data Sheet

iEthernet W5200

PPPALGO(Authentication Algorithm in PPPoE mode)[R][0x001E][0x00]

This register notifies authentication algorithm in PPPoE mode. For detailed information,

please refer to PPPoE application note.

VERSIONR (W5200 Chip Version Register)[R][0x001F][0x03]

This register is the W5200 chip version register.

PTIMER (PPP Link Control Protocol Request Timer Register) [R/W] [0x0028]

This register indicates the duration for sending LCP Echo Request. Value 1 is about 25ms.

Ex) in case that PTIMER is 200,

200 * 25(ms) = 5000(ms) = 5 seconds

PMAGIC (PPP Link Control Protocol Magic number Register) [R/W] [0x0029][0x00]

This register is used in Magic number option during LCP negotiation. Refer to the application

note, “How to connect ADSL”.

INTLEVEL (Interrupt Low Level Timer Register)[R/W][0x0030 – 0x0031][0x0000]

It sets Interrupt Assert wait time (I

AWT

). It configures nINT Low Assert waiting time

until the next interrupt.

AWT

= (INTLEVEL + 1) * PLL_CLK (when INTLEVEL > 0)

Figure 5 INTLEVEL Timing

a. At SOCKET 0, Receive Interrupt occurs (S0_IR(3) = ‘1’) and corresponding IR2 bit is set as ‘1’

(IR(S0_IR) = ‘1’). nINT signal is asserted low.

b. At SOCKET 1, Connected Interrupt occurs (S1_IR(0) = ‘1’) and corresponding IR2 bit set as ‘1’

(IR(S1_IR) = ‘1’).

c. The Host clears S0_IR1 (S0_IR = 0x00) and corresponding IR bit is automatically cleared

(IR(S0_IR) = ‘0’). nINT signal becomes High.

d. S0_IR is cleared. As IR2 is not 0x00, nINT should be asserted low right after 1PLL_CLK.

However, as INTLEVEL is 0x000F, the interrupt about IR is processed after I

AWT

(16 PLL_CLK).