Data Sheet

© Copyright 2012 WIZnet Co., Inc. All rights reserved.
15
iEthernet W5200
3.2 Socket registers
Note : n is socket number ( 0, 1, 2, 3, 4, 5, 6, 7 )
Address Register
0x4n00 Socket n Mode (Sn_MR)
0x4n01 Socket n Command (Sn_CR)
0x4n02 Socket n Interrupt (Sn_IR)
0x4n03 Socket n Status (Sn_SR)
0x4n04
0x4n05
Socket n SourcePort
(SN_PORT0)
(SN_PORT1)
0x4n06
0x4n07
0x4n08
0x4n09
0x4n0A
0x4n0B
Socket n Destination Hardware
Address
(Sn_DHAR0)
(Sn_DHAR1)
(Sn_DHAR2)
(Sn_DHAR3)
(Sn_DHAR4)
(Sn_DHAR5)
0x4n0C
0x4n0D
0x4n0E
0x4n0F
Socket 0 Destination IP Address
(Sn_DIPR0)
(Sn_DIPR1)
(Sn_DIPR2)
(Sn_DIPR3)
0x4n10
0x4n11
Socket 0 Destination Port
(Sn_DPORT0)
(Sn_DPORT1)
0x4n12
0x4n13
Socket 0 Maximum Segment Size
(Sn_MSSR0)
(Sn_MSSR1)
0x4n14
Socket 0 Protocol in IP Raw mode
(Sn_PROTO)
0x4n15 Socket n IP TOS (Sn_TOS)
0x4n16 Socket n IP TTL (Sn_TTL)
0x4n17
~
0x4n1D
Reserved
Address Register
0x4n1E
Receive Memory Size
(Sn_RXMEM_SIZE)
0x4n1F
Transmit Memory Size
(Sn_TXMEM_SIZE)
0x4n20
0x4n21
Socket 0 TX Free Size
(Sn_TX_FSR0)
(Sn_TX_FSR1)
0x4n22
0x4n23
Socket 0 TX Read Pointer
(Sn_TX_RD0)
(Sn_TX_RD1)
0x4n24
0x4n25
Socket 0 TX Write Pointer
(Sn_TX_WR0)
(Sn_TX_WR1)
0x4n26
0x4n27
Socket 0 RX Received Size
(Sn_RX_RSR0)
(Sn_RX_RSR1)
0x4n28
0x4n29
Socket 0 RX Read Pointer
(Sn_RX_RD0)
(Sn_RX_RD1)
0x4n2A
0x4n2B
Socket 0 RX Write Pointer
(Sn_RX_WR0)
(Sn_RX_WR1)
0x4n2C
Socket Interrupt Mask
(Sn_IMR)
0x4n2D
0x4n2E
Fragment Offset in IP header
(Sn_FRAG0)
(Sn_FRAG1)
0x4n30
~
0x4nFF
Reserved