iEthernet W5200 iEthernet W5200 Datasheet Version 1.2.5 http://www.wiznet.co.kr © Copyright 2012 WIZnet Co., Inc. All rights reserved.
iEthernet W5200 W5200 The W5200 chip is a Hardwired TCP/IP embedded Ethernet controller that enables easier internet connection for embedded systems using SPI (Serial Peripheral Interface). W5200 suits best for users who need Internet connectivity for application that uses a single chip to implement TCP/IP Stack, 10/100 Ethernet MAC and PHY. The W5200 is composed of a fully hardwired market-proven TCP/IP stack and an integrated Ethernet MAC & PHY.
iEthernet W5200 Target Applications The W5200 is well suited for many embedded applications, including: - Home Network Devices: Set-Top Boxes, PVRs, Digital Media Adapters - Serial-to-Ethernet: Access Controls, LED displays, Wireless AP relays, etc.
iEthernet W5200 Block Diagram © Copyright 2012 WIZnet Co., Inc. All rights reserved.
iEthernet W5200 Table of Contents 1 Pin Assignment............................................................................................ 8 1.1 MCU Interface Signals ....................................................................... 8 1.2 1.2 PHY Signals ............................................................................... 9 1.3 Miscellaneous Signals ...................................................................... 10 1.4 Power Supply Signals ...............................
iEthernet W5200 7.4.4 Transformer Characteristics ........................................................ 80 8 IR Reflow Temperature Profile (Lead-Free) ....................................................... 81 9 Package Descriptions .................................................................................. 82 Document History Information ............................................................................ 84 © Copyright 2012 WIZnet Co., Inc. All rights reserved.
iEthernet W5200 Table of Figure Figure 1 Pin Description W5200 .................................................................. 8 Figure 2 XTAL_VDD Reference Schematic .................................................... 11 Figure 3 Power Design ........................................................................... 11 Figure 4 Crystal Reference Schematic ........................................................ 12 Figure 5 INTLEVEL Timing ..............................................................
iEthernet W5200 RSV RSV RSV RSV RSV SPD DUP ANE GND VCC3V3 GND VCC1V8 36 35 34 33 32 31 30 29 28 27 26 25 Pin Assignment RSV 37 24 GNDA RSV 38 23 VCC3V3A RSV 39 22 GNDA nINT 40 21 RXIN 20 RXIP 19 GNDA nSCS 41 SCLK 42 MOSI 43 18 TXON MISO 44 17 TXOP PWDN 45 16 XTALVDD nRST 46 15 VCC3V3A VCC3V3 47 14 POWEROUT GND 48 13 GNDA 5 6 7 8 9 10 11 12 nLINKLED/M0 M3 RSV VCC1V8 GND GND VCC3V3A BIAS 3 4 2 XO nFDXLED/M2 nSPDLED/
iEthernet W5200 cleared by writing IR(Interrupt Register) or Sn_IR (Socket n-th Interrupt Register). All interrupts are maskable. This pin is active low. SCLK I 42 SPI CLOCK This pin is used to SPI Clock signal Pin when using SPI interface. MOSI I 43 SPI MASTER OUT SLAVE IN This pin is used to SPI MOSI signal pin when using SPI interface. MISO O 44 SPI MASTER IN SLAVE OUT This pin is used to SPI MISO signal pin. PWDN I 45 POWER DOWN ( Active HIGH ) This pin is used to power down pin.
iEthernet W5200 This pin selects 100M/10M Speed Mode. Low = 10M Speed Mode High = 100M Speed Mode This function activates only during reset period. 1.3 Miscellaneous Signals Symbol Type Pin No Description nFDXLED/M2 I 3, W5200 MODE SELECT nSPDLED/M1 4, Normal mode nLINKLED/M0 5 Other test modes are internal test mode. : 111 This function activates only during reset period M3 I 6 RSV - 7,32,33,34,35,36, 37,38,39 This pin should be pull-up.
I iEthernet W5200 XTALVDD 16 Figure 2 XTAL_VDD Reference Schematic Connect a capacitor of 10.1uF to the ground. ※ Refer to the ‘W5200E01-M3 Reference schematic Figure 3 Power Design Recommend for power design. 1. Locate decoupling capacitor as close as possible to W5200. 2. Use ground plane as wide as possible. © Copyright 2012 WIZnet Co., Inc. All rights reserved.
iEthernet W5200 3. If ground plane width is adequate, having a separate analog ground plane and digital ground plane is good practice. 4. If ground plane is not wide, design analog and digital ground planes as a single ground plane, rather than separate them. 1.5 Clock Signals Symbol Type Pin No XI I 1 Description 25MHz crystal input/output. A 25MHz crystal and Oscillator is used to connect these pins. XO O 2 XTAL OUT _ XTAL IN Figure 4 Crystal Reference Schematic 1.
iEthernet W5200 2 Memory Map W5200 is composed of Common Register, Socket Register, TX Memory, and RX Memory as shown below. W5200 Memory Map © Copyright 2012 WIZnet Co., Inc. All rights reserved.
iEthernet W5200 3 W5200 Registers 3.
iEthernet W5200 3.
iEthernet W5200 4 Register Descriptions 4.1 Common Registers MR (Mode Register) [R/W] [0x0000] [0x00] This register is used for S/W reset, ping block mode and PPPoE mode. 7 6 5 RST Bit 4 3 PB PPPoE Symbol 2 1 0 Description S/W Reset 7 RST If this bit is ‘1’, internal register will be initialized. It will be automatically cleared after reset.
0x0006 0x0007 0x0008 255 (0xFF) 255 (0xFF) 255 (0xFF) 0 (0x00) iEthernet W5200 0x0005 SHAR (Source Hardware Address Register) [R/W] [0x0009 – 0x000E] [0x00] This register sets up the Source Hardware address. Ex) In case of “00.08.DC.01.02.03” 0x0009 0x000A 0x000B 0x000C 0x000D 0x000E 0x00 0x08 0xDC 0x01 0x02 0x03 SIPR (Source IP Address Register) [R/W] [0x000F – 0x0012] [0x00] This register sets up the Source IP address. Ex) In case of “192.168.0.
iEthernet W5200 IMR (Interrupt Mask Register) [R/W] [0x0036] [0x00] The Interrupt Mask Register is used to mask interrupts. Each interrupt mask bit corresponds to a bit in the Interrupt Register (IR). If an interrupt mask bit is set, an interrupt will be issued whenever the corresponding bit in the IR is set. If any bit in the IMR is set as ‘0’, an interrupt will not occur though the bit in the IR is set.
iEthernet W5200 The timeout of W5200 can be configurable with RTR and RCR. W5200’s timeout has Address Resolution Protocol (ARP) and TCP retransmission timeout. At the ARP (Refer to RFC 826, http://www.ietf.org/rfc.html) retransmission timeout, W5200 automatically sends ARP-request to the peer’s IP address in order to acquire MAC address information (used for communication of IP, UDP, or TCP).
iEthernet W5200 PPPALGO(Authentication Algorithm in PPPoE mode)[R][0x001E][0x00] This register notifies authentication algorithm in PPPoE mode. For detailed information, please refer to PPPoE application note. VERSIONR (W5200 Chip Version Register)[R][0x001F][0x03] This register is the W5200 chip version register. PTIMER (PPP Link Control Protocol Request Timer Register) [R/W] [0x0028] This register indicates the duration for sending LCP Echo Request. Value 1 is about 25ms.
iEthernet W5200 IR2(W5200 SOCKET Interrupt Register)[R/W][0x0034][0x00] IR2 is the Register to notify W5200 SOCKET interrupt to the Host. If any interrupt occurs, the related bit of IR2 is set as ‘1’. When related Mask Bit is ‘1’, nINT signal is asserted low. nINT keeps low until all bits of Sn_IR becomes ‘0’. If all bits of Sn_IR become ‘0’, it becomes high automatically.
iEthernet W5200 PHYSTATUS(W5200 PHY status Register)[R/W][0x0035][0x00] PHYSTATUS is the Register to indicate W5200 status of PHY. Bit Symbol Description 7 Reserved Reserved 6 Reserved Reserved Link Status Register[Read Only] 5 This register indicates Link status.
iEthernet W5200 4.2 Socket Registers Sn 1_MR (Socket n-th-th Mode Register) [R/W] [0x4000+0x0n00] [0x00] 2 This register sets up socket option or protocol type for each socket. 7 6 MULTI Bit 5 4 ND / MC Symbol 3 2 1 0 P3 P2 P1 P0 Description Multicasting 0 : disable Multicasting 1 : enable Multicasting 7 MULTI It is applied only in case of UDP.
Reserved iEthernet W5200 4 Reserved Protocol 3 2 1 P3 P2 P1 Sets up corresponding socket as TCP, UDP, or IP RAW mode P P P P 3 2 1 0 0 0 0 0 Closed 0 0 0 1 TCP 0 0 1 0 UDP 0 0 1 1 IPRAW Meaning * In case of socket 0, MACRAW and PPPoE mode exist. 0 P0 P P P P 3 2 1 0 0 1 0 0 MACRAW 0 1 0 1 PPPoE Meaning S0_MR_MACRAW and S0_MR_PPPoE are valid only in SOCKET 0. S0_MR_PPPoE is temporarily used for PPPoE server connection/Termination.
iEthernet W5200 Sn_CR (Socket n-th Command Register) [R/W] [0x4001+0x0n00] [0x00] This is used to set the command for Socket n-th such as OPEN, CLOSE, CONNECT, LISTEN, SEND, and RECEIVE. After W5200 identifies the command, the Sn_CR register is automatically cleared to 0x00. Even though Sn_CR is cleared to 0x00, the command is still being processed. To verify whether the command is completed or not, please check the Sn_IR or Sn_SR registers.
iEthernet W5200 When a SYN/ACK packet is not received and TCPTO(Sn_IR(3)) is’1’ When a RST packet is received instead of a SYN/ACK packet Above three cases, Sn_SR is changed to SOCK_CLOSED.
iEthernet W5200 Register(Sn_RX_RD). Below commands are only valid for SOCKET 0 and S0_MR(P3:P0) = S0_MR_PPPoE. For more detail refer to the “How to use ADSL”. Value Symbol Description 0x23 PCON 0x24 PDISCON 0x25 PCR In each phase, it transmits REQ message. 0x26 PCN In each phase, it transmits NAK message. 0x27 PCJ In each phase, it transmits REJECT message. PPPoE connection begins by transmitting PPPoE discovery packet Closes PPPoE connection © Copyright 2012 WIZnet Co., Inc.
iEthernet W5200 Sn_IR (Socket n-th Interrupt Register) [R] [0x4002+0x0n00] [0x00] Sn_IR register provides information such as the type of interrupt (establishment, termination, receiving data, timeout) used in Socket n-th. When an interrupt occurs and the mask bit of Sn_IMR is ‘1’, the interrupt bit of Sn_IR becomes ‘1’. In order to clear the Sn_IR bit, the host should write the bit as ‘1’. When all the bits of Sn_IR is cleared (‘0’), IR(n) is automatically cleared.
iEthernet W5200 Sn_SR (Socket n-th Status Register) [R] [0x4003+0x0n00] [0x00] This register provides the status of Socket n-th. SOCKET status are changed when using the Sn_CR register or during packet transmission/reception. The table below describes the different states of Socket n-th. Value Symbol 0x00 SOCK_CLOSED Description It is the status that resource of SOCKETn is released.
SOCK_UDP iEthernet W5200 0x22 It is the status that SOCKETn is open as UDP mode. It is changed to SOCK_UDP when Sn_MR(P3:P0) is Sn_MR_UDP and OPEN command is performed. DATA packet can be transferred without connection that is necessary to TCP mode SOCKET. 0x32 SOCK_IPRAW The socket is opened in IPRAW mode. The SOCKET status is change to SOCK_IPRAW when Sn_MR (P3:P0) is Sn_MR_IPRAW and OPEN command is used. IP Packet can be transferred without a connection similar to the UDP mode.
iEthernet W5200 is observed when SEND command is performed at the SOCK_UDP or SOCK_IPRAW, or CONNECT command is performed at the SOCK_INIT. If hardware address is successfully acquired from destination (when ARP-response is received), it is changed to SOCK_UDP, SOCK_IPRAW or SOCK_SYNSENT. If it's failed and ARPTO occurs (Sn_IR(TIMEOUT)=‘1’), in case of UDP or IPRAW mode it goes back to the previous status(the SOCK_UDP or SOCK_IPRAW), in case of TCP mode it goes to the SOCK_CLOSED.
iEthernet W5200 Sn_PORT (Socket n-th Source Port Register) [R/W] [0x4004+0x0n00-0x4005+0x0n00] [0x0000] This register sets the Source Port number for each Socket when using TCP or UDP mode, and the set-up needs to be made before executing the OPEN command.
iEthernet W5200 At the UDP or IPRAW mode, Sn_DIPR sets as destination IP address to be used for transmitting UDP or IPRAW DATA packet before performing SEND or SEND_MAC command. Ex) In case of Socket 0 Destination IP address = 192.168.0.11, configure as below. 0x400C 0x040D 0x400E 0x040F 192 (0xC0) 168 (0xA8) 0 (0x00) 11 (0x0B) Sn_DPORT (Socket n-th Destination Port Register)[R/W][0x4010+0x0n00-0x4011+0x0n00] [0x00] The destination port number is set in the Sn_DPORT of Socket n-th.
iEthernet W5200 the data into the unit of MTU. MTU is called as MSS at the TCP mode. By selecting from HostWritten-Value and peer's MSS, MSS is set as smaller value through TCP connection process. Ex) In case of Socket 0 MSS = 1460(0x05B4), configure as below, 0x4012 0x4013 0x05 0xB4 Sn_PROTO (Socket n-th IP Protocol Register) [R/W] [0x4014+0x0n00] [0x00] It is a 1 byte register that sets the protocol number field of the IP header at the IP layer.
iEthernet W5200 Sn_RXMEM_SIZE(Socket n-th RX Memory Size Register) [R/W] [0x401E+0x0n00] [0x02] It configures the internal RX Memory size of each SOCKET. RX Memory size of each SOCKET is configurable in the size of 1, 2, 4, 8, and 16 Kbytes. 2Kbytes is assigned when reset. Sn_RXMEM_SIZESUM(sum of Sn_RXMEM_SIZE) of each SOCKET should be 16KB.
iEthernet W5200 Sn_TX_FSR (Socket n-th TX Free Size Register) [R] [0x4020+0x0n00-0x4021+0x0n00] [0x0800] It notifies the available size of the internal TX memory (the byte size of transmittable data) of Socket n-th. The host can’t write data as a size bigger than Sn_TX_FSR. Therefore, be sure to check Sn_TX_FSR before transmitting data, and if your data size is smaller than or the same as Sn_TX_FSR, transmit the data with SEND or SEND_MAC command after copying the data.
iEthernet W5200 Chip Base Address = 0x0000, 512(0x0200) bytes send 0xC000 Socket 7 (2K) 0xB800 Socket 6 (2K) 0xB000 Socket 5 (2K) 0xA800 Socket 4 (2K) 0xA000 Socket 3 (2K) 0x9800 Socket 2 (2K) 0x9000 Socket 1 (2K) 0x8800 Socket 0 (2K) 0x8000 0x8800 0x87EE If S0_TX_WR0 = 0x8FEE, Real Physical Address is 0x8000 + (0x8FEE & 0x07FF) = 0x87EE Socket 0 0x8000 0x8800 18 bytes Socket 0 0x87EE 0x8800 – 0x87EE = 0x12, 18 bytes write and remain 494 bytes.
iEthernet W5200 the transmission data to the upper-bound, and change the physical address to the gSn_TX_BASE. Next, write the rest of the transmission data.) After that, be sure to increase the Sn_TX_WR value as much as the data size that indicates the size of writing data. Finally, give SEND command to Sn_CR(Socket n-th Command Register). Refer to the psedo code of the transmission part on TCP Server mode if detail is needed.
iEthernet W5200 physical address(hereafter, we'll call get_start_address). Sn_RX_WR (Socket n-th RX Write Pointer Register)[R/W][(0xFE402A + 0xn00) – (0xFE402B + 0xn00)][0x0000] This register offers the location information to write the receive data. When reading this register, the user should read upper bytes (0x402A, 0x412A, 0x422A, 0x432A, 0x442A, 0x452A, 0x462A, 0x472A) first and lower bytes (0x402B, 0x412B, 0x422B, 0x432B, 0x442B, 0x452B, 0x462B, 0x472B) later to get the correct value.
iEthernet W5200 Sn_FRAG (Socket n-th Fragment Register)[R/W][0x402D+0x0n00-0x402E+ 0x0n100][0x4000] It sets the Fragment field of the IP header at the IP layer. W5200 does not support the packet fragment at the IP layer. Even though Sn_FRAG is configured, IP data is not fragmented, and not recommended either. It should be configured before performing OPEN command. Ex) Sn_FRAG0 = 0x4000 (Don’t Fragment) 0x402D 0x402E 0x40 0x00 © Copyright 2012 WIZnet Co., Inc. All rights reserved.
iEthernet W5200 5 Functional Descriptions By setting some register and memory operation, W5200 provides internet connectivity. This chapter describes how it can be operated. 5.1 Initialization Basic Setting For the W5200 operation, select and utilize appropriate registers shown below. 1. Mode Register (MR) 2. Interrupt Mask Register (IMR) 3. Retry Time-value Register (RTR) 4. Retry Count Register (RCR) For more information of above registers, refer to the “Register Descriptions.
iEthernet W5200 Set socket memory information This stage sets the socket tx/rx memory information. The base address and mask address of each socket are fixed and saved in this stage.
iEthernet W5200 Sn_TXMEM_SIZE(ch) = 2K, Chip base address = 0x0000 0xC000 Socket 7 Socket 6 Socket 5 Socket 4 Socket 3 Socket 2 Socket 1 Socket 0 0xB800 gS7_TX_BASE = 0xB800 gS7_TX_MASK = 0x07FF 0xB000 gS6_TX_BASE = 0xB000 gS6_TX_MASK = 0x07FF 0xA800 gS5_TX_BASE = 0xA800 gS5_TX_MASK = 0x07FF 0xA000 gS4_TX_BASE = 0xA000 gS4_TX_MASK = 0x07FF 0x9800 gS3_TX_BASE = 0x9800 gS3_TX_MASK = 0x07FF 0x9000 gS2_TX_BASE = 0x9000 gS2_TX_MASK = 0x07FF 0x8800 gS1_TX_BASE = 0x8800 gS1_TX_MASK = 0x07FF 0x8000
iEthernet W5200 5.2 Data Communications After the initialization process, W5200 can transmit and receive the data with others by ‘open’ the SOCKET of TCP, UDP, IPRAW, and MACRAW mode. The W5200 supports the independently and simultaneously usable 8 SOCKETS. In this section, the communication method for each mode will be introduced. 5.2.1 TCP The TCP is a connection-oriented protocol.
iEthernet W5200 5.2.1.1 TCP SERVER Figure 10 TCP SERVER Operation Flow SOCKET Initialization SOCKET initialization is required for TCP data communication. The initialization is opening the SOCKET. The SOCKET opening process selects one SOCKET from 8 SOCKETS of the W5200, and sets the protocol mode (Sn_MR) and Sn_PORT0 which is source port number (Listen port number in “TCP SERVER”) in the selected SOCKET, and then executes OPEN command.
iEthernet W5200 { START: Sn_MR = 0x01; // sets TCP mode Sn_PORT0 = source_port; // sets source port number Sn_CR = OPEN; // sets OPEN command /* wait until Sn_SR is changed to SOCK_INIT */ if (Sn_SR != SOCK_INIT) Sn_CR = CLOSE; goto START; } LISTEN Run as “TCP SERVER” by LISTEN command.
iEthernet W5200 ESTABLISHMENT : Check received data Confirm the reception of the TCP data. First method : { if (Sn_IR(RECV) == ‘1’) Sn_IR(RECV) = ‘1’; goto Receiving Process stage; /* In this case, if the interrupt of Socket n-th is activated, interrupt occurs. Refer to IR, IMR Sn_IMR and Sn_IR. */ } Second Method : { if (Sn_RX_RSR0 != 0x0000) goto Receiving Process stage; } The First method: set the Sn_IR(RECV) to ‘1’ whenever you receive a DATA packet.
iEthernet W5200 /* update destination_ptr */ dst_address += upper_size; /* copy left_size bytes of gSn_RX_BASE to destination_address */ left_size = len – upper_size; memcpy(gSn_RX_BASE, dst_address, left_size); } else { copy len bytes of source_ptr to destination_address */ memcpy(src_ptr, dst_ptr, len); } /* increase Sn_RX_RD as length of len */ Sn_RX_RD += len; /* set RECV command */ Sn_CR = RECV; } ESTABLISHMENT: Check send data / Send process The size of the transmit data cannot be larger than assign
iEthernet W5200 { /* first, get the free TX memory size */ FREESIZE: freesize = Sn_TX_FSR; if (freesize (gSn_TX_MASK + 1) ) { /* copy upper_size bytes of source_addr to destination_
iEthernet W5200 ESTABLISHMENT : Check disconnect-request(FIN packet) Check if the Disconnect-request(FIN packet) has been received. User can confirm the reception of FIN packet as below. First method : { if (Sn_IR(DISCON) == ‘1’) Sn_IR(DISCON)=‘1’; goto CLOSED stage; /* In this case, if the interrupt of Socket n-th is activated, interrupt occurs. Refer to IR, IMR Sn_IMR and Sn_IR.
iEthernet W5200 ESTABLISHMENT: Timeout The timeout can occur by Connect-request(SYN packet) or its response(SYN/ACK packet), the DATA packet or its response(DATA/ACK packet), the Disconnectrequest(FIN packet) or its response(FIN/ACK packet) and transmission all TCP packet. If it cannot transmit the above packets within ‘timeout’ which is configured at RTR and RCR, the TCP final timeout(TCP TO ) occurs and the state of Sn_SR is set to SOCK_CLOSED.
iEthernet W5200 5.2.1.2 TCP CLIENT It is same as TCP server except ‘CONNECT’ state. User can refer to the “5.2.1.1 TCP SERVER”. Figure 11 TCP CLIENT Operation Flow CONNECT Transmit the connect-request (SYN packet) to “TCP SERVER”.
iEthernet W5200 5.2.2 UDP The UDP is a Connection-less protocol. It communicates without “connection SOCKET.” The TCP protocol guarantees reliable data communication, but the UDP protocol uses datagram communication which has no guarantees of data communication. Because the UDP does not use “connection SOCKET,” it can communicate with many other devices with the known host IP address and port number.
iEthernet W5200 IP address. At this time, there is no need to get the destination hardware address about destination A, B and C, and also ARP TO is not occurred. Note: Broadcast IP => The Broadcast IP address can be obtained by performing a bit-wise logical OR operation between the bit complement of the subnet mask and the host’s IP address. ex> If IP:”222.98.173.123” and the subnet mask:“255.255.255.0”, broadcast IP is “222.98.173.255” Description Decimal Binary HOST IP 222.098.173.123 11011110.
iEthernet W5200 /* In this case, if the interrupt of Socket n-th is activated, interrupt occurs. Refer to IR, IMR Sn_IMR and Sn_IR. */ } Second Method : { if (Sn_RX_RSR0 != 0x0000) goto Receiving Process stage; } Receiving process Process the received UDP data in Internal RX memory. The structure of received UDP data is as below.
iEthernet W5200 /* update header_addr*/ header_addr += upper_size; /* copy left_size bytes of gSn_RX_BASE to header_address */ left_size = header_size – upper_size; memcpy(gSn_RX_BASE, header, left_size); /* update src_mask */ src_mask = left_size; } else { /* copy header_size bytes of get_start_address to header_address */ memcpy(src_ptr, header, header_size); /* update src_mask */ src_mask += header_size; } /* update src_ptr */ src_ptr = gSn_RX_BASE + src_mask; /* save remote peer information & received
iEthernet W5200 } /* increase Sn_RX_RD as length of len+ header_size */ Sn_RX_RD = Sn_RX_RD + header_size + get_size; /* set RECV command */ Sn_CR = RECV; } © Copyright 2012 WIZnet Co., Inc. All rights reserved.
iEthernet W5200 Check send data / sending process The size of DATA that the user wants to transmit cannot be larger than Internal TX memory. If it is larger than MTU, it is automatically divided by MTU unit and transmitted. The Sn_DIPR0 is set “255.255.255.255” when user wants to broadcast.
iEthernet W5200 /* set SEND command */ Sn_CR = SEND; } Check complete sending / Timeout To transmit the next data, user must check that the prior SEND command is completed. The larger the data size, the more time to complete the SEND command. Therefore, the user must properly divide the data to transmit. The ARP TO can occur when user transmits UDP data. If ARP TO occurs, the UDP data transmission has failed.
iEthernet W5200 5.2.2.2 Multicast The broadcast communication communicates with many and unspecified others. But the multicast communication communicates with many specified others who registered at a multicast-group. Suppose that A, B, and C are registered at a specified multicast-group. If user transmits data to multicast-group (contains A), B and C also receive the DATA for A. To use multicast communication, the destination list registers to multicast-group by using IGMP protocol.
iEthernet W5200 Sn_DHAR3 = 0x01; Sn_DHAR4 = 0x01; Sn_DHAR5 = 0x0B; Sn_DIPR0 = 211; /* set Multicast-Group IP address(211.1.1.
iEthernet W5200 if ( (dst_mask + len) > (gSn_TX_MASK + 1) ) { /* copy upper_size bytes of source_addr to destination_address */ upper_size = (gSn_TX_MASK + 1) – dst_mask; wizmemcpy((0x000000 + source_addr), (0xFE0000 + dst_ptr), upper_size); /* update source_addr*/ source_addr += upper_size; /* copy left_size bytes of source_addr to gSn_TX_BASE */ left_size = len – upper_size; wizmemcpy( source_addr, gSn_TX_BASE, left_size); } else { /* copy len bytes of source_addr to dst_ptr */ wizmemcpy( source_addr, ds
iEthernet W5200 5.2.3 IPRAW IPRAW is data communication using TCP, UDP, and IP layers, which are the lower protocol layers. IPRAW supports IP layer protocol such as ICMP (0x01) and IGMP (0x02) according to the protocol number. The ‘ping’ of ICMP or IGMP v1/v2 is already included in W5200 by hardware logic. But if the user needs, the host can directly process the IPRAW by opening the Socket n-th to IPRAW.
iEthernet W5200 /* sets IP raw mode */ Sn_MR = 0x03; /* sets OPEN command */ Sn_CR = OPEN; /* wait until Sn_SR is changed to SOCK_IPRAW */ if (Sn_SR != SOCK_IPRAW) Sn_CR = CLOSE; goto START; } Check received data Refer to the “5.2.2.1 Unicast & Broadcast.” Receiving process Process the IPRAW data which is received in internal RX memory. The structure of received IPRAW data is as below.
iEthernet W5200 5.2.4 MACRAW The MACRAW communication is based on Ethernet MAC, and it can flexibly use upper layer protocol to suit the host’s needs. The MACRAW mode can only be used with a SOCKET. If the user uses the SOCKET in MACRAW mode, not only can it use the SOCKET1~7 in the ‘Hardwired TCP/IP stack’, but it can also be used as a NIC (Network Interface Controller). Therefore, any SOCKET1~7 can be used with ‘Software TCP/IP stack’.
iEthernet W5200 SOCKET Initialization Select the SOCKET and set the SN_MR(P3:P0) to MACRAW mode. Then execute the ‘OPEN’ command. After the ‘OPEN’ command, if the Sn_SR is successfully changed to ‘SOCK_MACRAW’, the SOCKET initialization is completed. Since all information about communication (Source hardware address, Source IP address, Source port number, Destination hardware address, Destination IP address, Destination port number, Protocol header, etc.
iEthernet W5200 src_ptr = gSn_RX_BASE + src_mask; // src_ptr is physical start address /* get the received size */ len = get_Byte_Size_Of_Data_packet // get Byte size of DATA packet from Packet-INFO /* if overflow SOCKET RX memory */ If((src_mask + len) > (gSn_RX_MASK + 1)) { /* copy upper_size bytes of get_start_address to destination_address */ upper_size = (gSn_RX_MASK + 1) – src_mask; memcpy(src_ptr, dst_addr, upper_size); /* update destination_address */ dst_addr += upper_size; /* copy left_size byt
iEthernet W5200 { START: /* sets MAC raw mode with enabling MAC filter */ S0_MR = 0x44; /* sets OPEN command */ S0_CR = OPEN; /* wait until Sn_SR is changed to SOCK_MACRAW */ if (Sn_SR != SOCK_MACRAW) S0_CR = CLOSE; goto START; } ▪If the free size of the internal RX memory is smaller than ‘1528 - Default MTU(1514)+PACKET INFO(2) + DATA packet(8) + CRC(4)’, close the SOCKET and process all received data. Then reopen the SOCKET.
iEthernet W5200 else { /* copy len bytes of src_ptr to destination_address */ memcpy(src_ptr, dst_addr, len); } /* increase Sn_RX_RD as length of len */ Sn_RX_RD += len; /* extract 4 bytes CRC from internal RX memory and then ignore it */ memcpy(src_ptr, dst_addr, len); /* calculate the size of remained data in internal RX memory*/ recved_size = recved_size – 2 – len – 4; } /* Reopen the SOCKET */ /* sets MAC raw mode with enabling MAC filter */ S0_MR = 0x44; /* or S0_MR = 0x04 */ /* sets OPEN command */
iEthernet W5200 dst_ptr = gSn_TX_BASE + dst_mask; // dst_ptr is physical start address /* if overflow SOCKETTX memory */ if ( (dst_mask + len) > (gSn_TX_MASK + 1) ) {/* copy upper_size bytes of source_addr to destination_address */ upper_size = (gSn_TX_MASK + 1) – dst_mask; memcpy(src_ptr, dst_addr, upper_size); /* update source_addr*/ source_addr += upper_size; /* copy left_size bytes of source_addr to gSn_TX_BASE */ left_size = len – upper_size; memcpy(src_ptr, dst_addr, left_size); } else {/* copy len
iEthernet W5200 6 External Interface For the communication with MCU, W5200 provides SPI I/F modes. For the communication with Ethernet PHY, MII is used. 6.1 SPI (Serial Peripheral Interface) mode Serial Peripheral Interface Mode uses only four pins for data communication. Four pins are nSCS, SCLK, MOSI, and MISO. SPI Master SPI Slave Vcc External MCU W5200 (Hardwired TCP/IPCore) M3 SPI1_NSS /SCS SPI1_SCK SCLK SPI1_MOSI MOSI SPI1_MISO MISO Figure 18 SPI Interface 6.
iEthernet W5200 6.3 Process of using general SPI Master device 1. Configure Input/Output direction on SPI Master Device pins. 2. Configure nSCS as ‘High’ on inactive 3. Write target address for transmission on SPDR register (SPI Data Register). 4. Write OP code and data length for transmission on SPDR register. 5. Write desired data for transmission on SPDR register. 6. Configure nSCS as ‘Low’ (data transfer start) 7. Wait for reception complete 8.
iEthernet W5200 READ Processing The READ Processing Sequence Diagram is shown in Figure 20. The READ processing is entered by driving nSCS low, followed by the Address, the OP code, the Data Length and the Dummy data byte on MOSI. And then W5200 read the data byte on MISO. The Address, the OP/Data Length Sequence Diagram and the Data are shown in Figure 19. The OP code (OP) is defined type of the READ OP and WIRTE OP. On OP = 0, the read operation is selected.
CSoff(); iEthernet W5200 ISR_DISABLE(); // Interrupt Service Routine disable // CS=0, SPI start // SpiSendData SpiSendData(((addr+idx) & 0xFF00) >> 8); SpiSendData((addr+idx) & 0x00FF); // Address byte 1 // Address byte 2 // Data write command + Data length upper 7bits SpiSendData((data_read_command| ((data_len& 0x7F00) >> 8))); // Data length bottom 8bits SpiSendData((data_len& 0x00FF)); // Read data:On data_len> 1, Burst Read Processing Mode.
iEthernet W5200 WRITE Processing The WRITE Processing Sequence Diagram is shown in Figure 21.The WRITE processing is entered by driving nSCS low, followed by the Address, the OP code, the Data Length, and the Data byte on MOSI. In W5200 SPI mode, the Byte WRITE processing and the Burst WRITE processing are provided. The Byte WRITE processing takes 4 instructions which is consist of the 16-bit Address, the 1-bit OP code(0x1), the 15-bit Data length and 8-bit Data.
iEthernet W5200 CSoff();// CS=0, SPI start SpiSendData(((addr+idx) & 0xFF00) >> 8); SpiSendData((addr+idx) & 0x00FF); // Address byte 1 // Address byte 2 // Data write command + Data length upper 7bits SpiSendData((data_write_command | ((data_len& 0x7F00) >> 8))); // Data length bottom 8bits SpiSendData((data_len& 0x00FF)); // Write data: On data_len> 1, Burst Write Processing Mode.
iEthernet W5200 7 Electrical Specifications 7.1 Absolute Maximum Ratings Symbol Parameter Rating Unit VDD DC Supply voltage -0.5 to 3.63 V VIN DC input voltage -0.5 to 5.5 (5V tolerant) V IIN DC input current ±5 mA TOP Operating temperature -40 to 85 °C TSTG Storage temperature -55 to 125 °C *COMMENT: Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage. 7.
iEthernet W5200 7.4 AC Characteristics 7.4.1 Reset Timing TRC nRST TPL PLOCK (Internal) Figure 23 Reset Timing Symbol Description Min Max TRC Reset Cycle Time 2 us - TPL nRST internal PLOCK - 150 ms 7.4.2 Crystal Characteristics Parameter Range Frequency 25 MHz Frequency Tolerance (at 25℃) ±30 ppm Shunt Capacitance 7pF Max Drive Level 59.12uW/MHz Load Capacitance 27pF Aging (at 25℃) ±3ppm / year Max © Copyright 2012 WIZnet Co., Inc. All rights reserved.
iEthernet W5200 7.4.
iEthernet W5200 7.4.4 Transformer Characteristics Parameter Transmit End Receive End Turn Ratio 1:1 1:1 Inductance 350 uH 350 uH Figure 25 Transformer Type In case of using internal PHY mode, be sure to use symmetric transformer in order to support Auto MDI/MDIX(Crossover). © Copyright 2012 WIZnet Co., Inc. All rights reserved.
iEthernet W5200 8 IR Reflow Temperature Profile (Lead-Free) Moisture Sensitivity Level : 3 Dry Pack Required: Yes Average Ramp-Up Rate 3° C/second max.
iEthernet W5200 9 Package Descriptions Figure 27 Package Dimensions Note: 1. All dimensions are in millimeters. 2. Die thickness allowable is 0.0304 mm MAXMUM (0.012 Inches MAXIMUM) 3. Dimension & tolerances conform to same Y14.5M. -1994. 4. Dimension applies to plated terminal and is measured between 0.20 and 0.25mm from terminal tip. 5. The pin #1 identifier must be placed on the top surface of the package by using indentation mark or other feature of package body. 6.
iEthernet W5200 7. Package warpage max 0.08 mm. 8. Applied for exposed pad and terminals. Exclude embedding part of exposed pad from measuring 9. Applied only to terminals 10. Package corners unless otherwise specified are R0.175+/- 0.025mm © Copyright 2012 WIZnet Co., Inc. All rights reserved.
iEthernet W5200 Document History Information Version Date Descriptions Ver. 1.0.0 Mar2011 Released with W5200 Launching Ver. 1.1.0 13MAR2011 Changed IMR address (0x16 to 0x36) (P.14, P.18) Changed IMR2 address (0x36 to 0x16) (P.14, P.22) Ver. 1.2.0 22APR2011 Fixed the description of RSV at 1.3 Miscellaneous Signals (P.10) Fixed the values of typical at 7.3 power dissipation (P.77) Added the values of maximum at 7.3 power dissipation (P.77) Fixed the description of RSV at 1.
