Data Sheet

CC1101
SWRS061B Page 64 of 93
0x03: FIFOTHR – RX FIFO and TX FIFO Thresholds
Bit Field Name Reset R/W Description
7:6 Reserved 0 R/W Write 0 for compatibility with possible future extensions
6 ADC_RETENTION 0 R/W 0: TEST1 = 0x31 and TEST2 = 0x88 when waking up from SLEEP
1: TEST1 = 0x35 and TEST2 = 0x81 when waking up from SLEEP
5:4 CLOSE_IN_RX [1:0] 0 (00) R/W For more details, please see DN010 [10]
Setting RX Attenuation, Typical Values
0 (00) 0dB
1 (01) 6dB
2 (10) 12dB
3 (11) 18dB
3:0 FIFO_THR[3:0] 7 (0111) R/W Set the threshold for the TX FIFO and RX FIFO. The threshold is
exceeded when the number of bytes in the FIFO is equal to or higher
than the threshold value.
Setting Bytes in TX FIFO Bytes in RX FIFO
0 (0000) 61 4
1 (0001) 57 8
2 (0010) 53 12
3 (0011) 49 16
4 (0100) 45 20
5 (0101) 41 24
6 (0110) 37 28
7 (0111) 33 32
8 (1000) 29 36
9 (1001) 25 40
10 (1010) 21 44
11 (1011) 17 48
12 (1100) 13 52
13 (1101) 9 56
14 (1110) 5 60
15 (1111) 1 64
0x04: SYNC1 – Sync Word, High Byte
Bit Field Name Reset R/W Description
7:0 SYNC[15:8] 211 (0xD3) R/W 8 MSB of 16-bit sync word
0x05: SYNC0 – Sync Word, Low Byte
Bit Field Name Reset R/W Description
7:0 SYNC[7:0] 145 (0x91) R/W 8 LSB of 16-bit sync word