Data Sheet
CC1101
SWRS061B Page 48 of 93
23 Voltage Regulators
CC1101
contains several on-chip linear voltage
regulators, which generate the supply voltage
needed by low-voltage modules. These
voltage regulators are invisible to the user, and
can be viewed as integral parts of the various
modules. The user must however make sure
that the absolute maximum ratings and
required pin voltages in Table 1 and Table 13
are not exceeded. The voltage regulator for
the digital core requires one external
decoupling capacitor.
Setting the CSn pin low turns on the voltage
regulator to the digital core and starts the
crystal oscillator. The SO pin on the SPI
interface must go low before the first positive
edge of SCLK. (setup time is given in Table
16).
If the chip is programmed to enter power-down
mode, (SPWD strobe issued), the power will be
turned off after CSn goes high. The power and
crystal oscillator will be turned on again when
CSn goes low.
The voltage regulator output should only be
used for driving the
CC1101
.
24 Output Power Programming
The RF output power level from the device
has two levels of programmability, as
illustrated in Figure 22. Firstly, the special
PATABLE register can hold up to eight user
selected output power settings. Secondly, the
3-bit FREND0.PA_POWER value selects the
PATABLE entry to use. This two-level
functionality provides flexible PA power ramp
up and ramp down at the start and end of
transmission, as well as ASK modulation
shaping. All the PA power settings in the
PATABLE from index 0 up to the
FREND0.PA_POWER value are used.
The power ramping at the start and at the end
of a packet can be turned off by setting
FREND0.PA_POWER to zero and then
program the desired output power to index 0 in
the PATABLE.
If OOK modulation is used, the logic 0 and
logic 1 power levels shall be programmed to
index 0 and 1 respectively.
Table 30 contains recommended PATABLE
settings for various output levels and
frequency bands. Using PA settings from 0x61
to 0x6F is not recommended. See Section
10.6 on page 27 for PATABLE programming
details.
Table 31 contains output power and current
consumption for default PATABLE setting
(0xC6). PATABLE must be programmed in
burst mode if you want to write to other entries
than PATABLE[0].
Note that all content of the PATABLE, except
for the first byte (index 0) is lost when entering
the SLEEP state.