Data Sheet

CC1101
SWRS061B Page 46 of 93
FIFO is read over the SPI interface, the RX
FIFO pointer is not properly updated and the
last read byte is duplicated. To avoid this
problem one should never empty the RX FIFO
before the last byte of the packet is received.
For packet lengths less than 64 bytes it is
recommended to wait until the complete
packet has been received before reading it out
of the RX FIFO.
If the packet length is larger than 64 bytes the
MCU must determine how many bytes can be
read from the RX FIFO
(RXBYTES.NUM_RXBYTES-1) and the following
software routine can be used:
1. Read RXBYTES.NUM_RXBYTES
repeatedly at a rate guaranteed to be at
least twice that of which RF bytes are
received until the same value is returned
twice; store value in
n.
2. If n < # of bytes remaining in packet, read
n-1 bytes from the RX FIFO.
3. Repeat steps 1 and 2 until n = # of bytes
remaining in packet.
4. Read the remaining bytes from the RX
FIFO.
The 4-bit FIFOTHR.FIFO_THR setting is used
to program threshold points in the FIFOs.
Table 29 lists the 16 FIFO_THR settings and
the corresponding thresholds for the RX and
TX FIFOs. The threshold value is coded in
opposite directions for the RX FIFO and TX
FIFO. This gives equal margin to the overflow
and underflow conditions when the threshold
is reached.
A signal will assert when the number of bytes
in the FIFO is equal to or higher than the
programmed threshold. This signal can be
viewed on the GDO pins (see Table 33 on
page 55).
Figure 21 shows the number of bytes in both
the RX FIFO and TX FIFO when the threshold
signal toggles, in the case of FIFO_THR=13.
Figure 20 shows the signal as the respective
FIFO is filled above the threshold, and then
drained below.
53 54 55 56 5354555657
6 7 8 9 678910
NUM_RXBYTES
GDO
NUM_TXBYTES
GDO
Figure 20: FIFO_THR=13 vs. Number of
Bytes in FIFO (GDOx_CFG=0x00 in RX and
GDOx_CFG=0x02 in TX)
FIFO_THR
Bytes in TX FIFO Bytes in RX FIFO
0 (0000) 61 4
1 (0001) 57 8
2 (0010) 53 12
3 (0011) 49 16
4 (0100) 45 20
5 (0101) 41 24
6 (0110) 37 28
7 (0111) 33 32
8 (1000) 29 36
9 (1001) 25 40
10 (1010) 21 44
11 (1011) 17 48
12 (1100) 13 52
13 (1101) 9 56
14 (1110) 5 60
15 (1111) 1 64
Table 29: FIFO_THR Settings and the
Corresponding FIFO Thresholds
56 bytes
8 bytes
Overflow
margin
Underflow
margin
F
I
F
O
_
T
H
R
=
1
3
F
I
F
O
_
T
H
R
=
1
3
RXFIFO TXFIFO
Figure 21: Example of FIFOs at Threshold