Service Manual

MM-E 2072-09333-00
HOLE_157
DR5
1
G
ND
G
ND
_S
LOT
_3
S
H5
GND
1
GND
1
LOW_RF
3.3V
AMB _TEMP
A_D_DATA
CONVST
D2A_OVEN_SEL
DIGITAL_16.8Mhz
DSM_AGC_EN
DSM_OUTPUT_1.05Mhz
FRAC_N_1_SEL
FRAC_N_2_SEL
L OW_RF_SEL
NOISE_CONTROL
PENDULL UM_SEL
PTT_IN
PWR_LEVEL
SPI_CLK
SPI_CLK _UP
SPI_DATA _OUT
SPI_DATA _OUT_UP
SR_CLK
SR_DATA
SYNTH_LOCK
VCO1_SEL
VCO2_SEL
VCO3_SEL
1
G
ND
GND
_EDGE_2
SH8
1
G
ND
S
H1
G
ND_SL OT_1
GND
1
S
H2
G
ND
_S
LOT
_5
GND
1
GND
_EDGE_3
ED
G
E1
GND
1
SH3
GND_SLOT_2
GND
1
SH4
GND_SLOT_6
SR_DATA
SYNTH_LOCK
VCO1_SEL
VCO2_SEL
VCO3_SEL
GND
_EDGE_1
SH6
1
G
ND
S
H7
G
ND
_S
LOT
_4
CPU
_
AUD
IO
3.3V
AMB _TEMP
A_D_DATA
CONVST
D2A_OVEN_SEL
DIGITAL_16 .8Mhz
DSM_AGC_EN
DSM_OUTPUT_1.05Mhz
FRAC_N_1_SEL
FRAC_N_2_SEL
LOW_RF_SEL
NOISE_CONTROL
PENDULL UM_SEL
PTT_OUT
PWR_LEVEL
RESET
SPI_CLK
SPI_CL K_UP
SPI_DA TA_OUT
SPI_DATA_OUT_UP
SR_CLK
HOLE_138
DR4
1
G
ND
DR1
1
G
ND
HOLE_138
DR2
1
G
ND
DR6
1
G
ND
HOLE_138
DR3
1
G
ND
HOLE_138 HOLE_157
Figure A-1.A. LORD Module, Schematic Circuit Diagram (Sheet 1 of 15 – Module Interconnection Diagram)
A-3/A-4