Service Manual

MM-E 2072-09333-00
2-28
a. PLL Control. Synthesizer 1 is a PLL using the frequency synthesizer control subsystem U6075
to generate a control voltage for one of the three VCOs used to cover the required frequency
range.
The control voltage is derived by the loop filter C2142, C2117, R2047, R2045, C2118, which
integrates the pulses appearing at the phase/frequency detector output, CP. These pulses are
generated by comparing the reference frequency connected to the OSC_IN input with a sample
of the selected VCO output, connected to the FIN input. Both signals undergo frequency
division inside U6075: the division ratio is determined by the data carried by the SR_DATA
line, when the PLL_1_SEL line rises to a high level.
b. VCO Selection. The VCO corresponding to the current operating frequency range is enabled by
a high level applied on the corresponding FILT_VCO_SEL line. A high level also turns on the
corresponding PIN diode, CR2001 to CR2003, thereby connecting the VCO output signal to the
amplifier, Q2006. A sample of the Q2006 output signal is connected to the FIN input of U6075,
to close the PLL loop.
c. Output Circuits. The output signal of Q2006 is also applied to the amplifier U2002. U2002
output signal drives the clock input of the divider by 2, U2009. U2009 output is filtered by a
bandpass filter, and connected via the FIRST_INJ line to the first mixer.
d. The regulated supply voltages needed by the synthesizer 1 are provided by two linear regulators,
built around U2004 and U6024.
e. The FO_LD lock indication provided by U6075 is combined by CR2000 with the lock
indication of U6076, to obtain the SYNTH_LOCK synthesizer status line (high level indicates
loss of lock).
2-4.7.3 Synthesizer 2
Figure 2-14 shows the functional block diagram of the synthesizer 2.
U6076
Reference
Divider
Phase,
Frequency
and
Lock Detector
Programmable
Divider
CP
FIN
Loop
Filter
VCO 4
Q9060
Amplifier
Q2007
Amplifier
U2003
Filter
16.8 MHz
TX_SEC_INJ
PLL2 Control Data
+5V Regulator
U6025
SW_A+RF
VOS2
FO_LD
Lock Indication
OSC_IN
8
U2010
.
.
TX: 368.4 MHz, 10 kHz steps
RX: 352.4 to 369.2 MHz, 10 kHz steps
TX: 46.15 MHz, 1.25 kHz steps
RX: 44.05 to 46.15 MHz, 1.25 kHz steps
Figure 2-14. Synthesizer 2, Functional Block Diagram
a. PLL Control. Synthesizer uses a PLL control built around U6076, which is similar to U6075
(see para. 2-4.7.2.a). The control voltage generated by the loop filter is applied to the frequency
control input of VCO 4.
b. VCO 4 output signal is amplified by Q2007. A sample of the Q2007 output signal is connected
to the FIN input of U6076, to close the PLL loop.
c. Output Circuits. The output signal of Q2007 is also applied to the amplifier U2003. U2003
output signal drives the clock input of the divider by 8, U2010. U2010 output is filtered by a
bandpass filter, and connected via the TX_SEC_INJ line to the second mixer.
d. The regulated supply voltage needed by the synthesizer 2 is provided by a linear regulator built
around U6025.