Service Manual

MM-E 2072-09333-00
2-27
U5008 can measure the voltage proportional to the ambient temperature near the oscillator (provided
by the thermistor R3023) by means of its internal A/D converter, through the AMB_TEMP line
connected to the AN5/PDA5 input.
2-4.7.1.2 OCXO Option
U3002 is an ovenized crystal oscillator, which includes circuits that enable to maintain the oscillator at
a constant temperature, higher than the ambient. The power for the OCXO is provided by a +10V
linear voltage regulator, U3004.
a. Temperature Control Loop. When U3002 is installed, its temperature indication output,
TEMP_SENSE, is compared by a differential amplifier built around U3000 with the
OVEN_TEMP_CNTL voltages provided by D/A converter U1104. The resulting error voltage
is amplified, and used to drive, via Q3000, the HEAT_CONT input of the OCXO. The current
flowing through Q3000 is monitored by the OCXO using R3024, R3025, via the CUR_SENSE
input.
b. Frequency Adjustment. The microcontroller U5008 adjusts the OCXO frequency in accordance
with the stored calibration data. The required information is sent via the SPI_DATA_OUT, and
it is latched in the D/A converter U3010 on the rising edge of the PENDULLUM_SEL line. The
resulting DC voltage is applied to the D2A_FREQ input of U3002.
2-4.7.1.3 Distribution of 16.8 MHz Reference Frequency
The squarewave provided by U3001 or U3002 is connected to two amplifiers, Q3001 and Q3002:
a. The signal developing at the collector of Q3001 is filtered by a bandpass filter and applied on
the IF_16.8MHz line. The IF_16.8MHz line is converted to a squarewave by the Schmitt trigger
in U1109, for use as the frequency reference for synthesizer 2; in addition, the signal passes
through an additional Schmitt trigger in U1109 to the DSP_16.8MHz line, for the DSP
subsystem.
The output signal of the Schmitt trigger is also applied to the clock inputs of the 4-bit
programmable counters U1113, U1114, which operate as a divider by 39 (para. 2-4.6.3).
b. Q3002 receives the signal through a bandpass filter, and provides the SINE_16.8MHz reference
signal for synthesizer 1.
2-4.7.2 Synthesizer 1
The functional block diagram of synthesizer 1 is shown in Figure 2-13.
U6075
Reference
Divider
Phase,
Frequency
and
Lock
Detector
Programmable
Divider
CP
FIN
Loop
Filter
SINE_16.8MHz
PLL1 Control Data
+5V Regulator
U6024
+6V Regulator
U2004
SW_A+RF
VOS
VP1
FO_LD
Lock Indication
OSC_IN
VCO 3
126-150.2 MHz
Q9040, Q9065
VCO 2
107-126.5 MHz
Q9020, Q9064
VCO 1
90.4-107 MHz
Q9000, Q9063
Filter
FIRST_INJ
VCO Selection
(FILT_VCO_SEL)
2
U2009
.
.
PIN Diode Switch
CR2001-CR2003
VCO Bank
Amplifier
Q2006
Amplifier
U2002
90.4 to 150.2 MHz,
in 17.5 kHz steps
46.7 to 75.1 MHz,
in 8.75 kHz steps
Figure 2-13. Synthesizer 1, Functional Block Diagram