Service Manual

MM-E 2072-09333-00
2-21
Section II. CIRCUIT ANALYSIS
2-4. LORD MODULE
The schematic circuit diagram of the LORD module is shown in Figure A-1, and the module block
diagram is shown in Figure 2-12.
2-4.1 Audio Subsystem
Refer to Figure A-1.C. The audio subsystem uses the 8V_AUDID_ISB voltage, provided by the linear
voltage regulator U6098, and a bias voltage, 4V_AUDID_BIAS, generated by part of U4000.
2-4.1.1 Audio Transmit Path
a. Microphone Signal Path. The MIC_IN signal from the front panel passes through the analog
switch in U6085 to an amplifier, followed by a voiceband bandpass filter in U4003. The
resulting signal is sent to the codec U6040 via the MIC line.
b. EXT_TX_AUDIO Signal Path. The EXT_TX_AUDIO signal from the ACCESSORY
connector is converted to a single-ended signal by an amplifier in U4000, and then is connected
through the analog switches in U6085 to the microphone signal path.
2-4.1.2 Audio Receive Path
a. SPKR Signal Path. The RX_AUDIO signal received from the codec U6040 is converted to a
single-ended signal by an amplifier in U4003, passes through an analog switch in U6084 to the
digitally-controlled potentiometer U6081, which serves as a volume control.
U6081 output is connected by another section of U6084 to an amplifier in U4000, which drives
the audio power amplifier U4002. U4002 balanced output signal, SPKR, is sent to the front
panel assembly.
b. Baseband and Modem Signal Outputs. The single-ended RX_AUDIO output signal is directly
connected to a driver built around U6082, which drives the balanced EXT_RX_DATA lines in
the ACCESSORY connector.
In addition, the signal can also be connected via analog switches in U6084 to another driver
built around U6082, which drives the balanced EXT_RX_AUDIO lines in the ACCESSORY
connector.
2-4.2 DSP Subsystem
Refer to Figure A-1.D.
The main supply voltage for the DSP subsystem, +3.3V, is provided by a linear voltage regulator,
U6097.
2-4.2.1 Transmit Path
a. The modulation signal, MIC, is applied to the input, INP, of the analog/digital conversion
section of the coder, U6040. This section includes an anti-aliasing filter, followed by a
programmable gain amplifier. The resulting signal is converted to a digital data stream, DOUT,
at a rate determined by the MCLK (main clock) signal received from a timer, TI02, in the DSP
U6042. The codec operates in the pulse mode, that is, it generates a continuous stream of bits
that represent the modulation signal.
The codec data stream, DOUT, and the associated clock, SCLK, are supplied to the enhanced
synchronous serial interface (ESSI 1) of the DSP.
b. DSP Functions. The DSP, U6042, is a digital signal processor with a 24-bit core. Its clock
signal is 16.8 MHz, received from the frequency reference generator via the DSP_16.8MHz. It
is controlled by the microcontroller, U5008, via the data and address buses, which connect to