User`s guide

Elan Digital Systems Ltd. 27 AD125 USER’S GUIDE
3.6 DAC PROGRAMMING
The DACs on the MF series are loaded serially using the upper four
digital I/O lines (which are no longer accessible on the MF series).
The following code fragment shows how to set DAC codes up:
void EXPORTFUNCTION DLL_SetDtoACodes(unsigned char skt,unsigned short code1, unsigned
short code2)
{ //pass in either code as 0xFFFF to load
previous DAC code
unsigned char d,dout,bit,cmds[100],cmdct=0;
//Note: if there are two threads altering the DIO pins at the same time and this
routine
//is interrupted by the other and alters the state of the bottom 4 DIOs then this
routine
//will revert them back to their states as read by the following line of code...
d = DLL_ReadIOPins(skt) & (unsigned char)0x0f; //leave lower 4 DIOs alone
//A semaphore scheme to interlock accesses could be added if this is a problem.
if (code1 == 0xffff)
code1 = DtoACode[0][skt]; //use last code if ffff passed in
if (code2 == 0xffff)
code2 = DtoACode[1][skt];
DtoACode[0][skt] = code1; //record the state for DtoA1
DtoACode[1][skt] = code2; //record the state for DtoA2
code1 <<= 1; //require 3 bit opcode + 12 bit data + 1 stop bit so move data +
opcode one place left
code2 <<= 1; //to make the stop bit
//For speed this routine "compiles" a list of byte wide Digital IO data and blats
its in
//one go using a block write.
cmds[cmdct++] = d; //set nCS low
for(bit=0;bit<16;bit++)
{
cmds[cmdct++] = dout = d | (unsigned char)((code1 & (unsigned short)0x8000) >>
11) | (unsigned char)((code2 & (unsigned short)0x8000) >> 10);
cmds[cmdct++] = dout | (unsigned char)0x40; //set clk high
code1 <<= 1; //next bits, NB msbit goes out first
code2 <<= 1;
}
cmds[cmdct++] = dout; //set clk low after last bit
if (DtoAWFGMode[skt] == INACTIVE)
cmds[cmdct++] = dout | (unsigned char)0x80; //set nCS high to update DACs, or
leave it
//low so that pacer can
//return it high automatically
when in WFG //mode
ByteWriteIOPort(io_win[skt],IODATA); //send the index for the digital IO
data
BlockWriteIOPort((unsigned short)(io_win[skt]+1),1,cmds,cmdct); //then blat the
data bytes //in a burst
}
One extra feature for the two DACs is their ability to be updated in
synchronism with an ADC event. After shifting in the DAC codes it
is usual to return the “nCS” line to the DACs high to affect the
update (the line is common to both). However, if this line is left low
and “waveform generation mode” is selected the “nCS” line will be
returned high automatically the next time the ADC section of the
card generates an interrupt. This can be used to “pace” the DAC