User`s guide

Elan Digital Systems Ltd. 24 AD125 USER’S GUIDE

To actually use interrupts the HOST controller will have to be

configured to route the IREQ signal to one of the PC’s interrupt

channels.

Note that all conditions that cause an interrupt can also be polled for

in software; that is, you do not have to use interrupts. This is

because the state of the internal Flip-Flop that latches the interrupt

state can be read via IODIR REGISTER Bit 4: 0→INTERRUPT

PENDING, 1→NO INTERRUPT.

The interrupt from the AD125 is latched. It must be cleared before

another interrupt can be generated. To clear it read from the SRAM

buffer. It can also be cleared by a soft or hard reset or by pulsing the

SELCTRD bit in SETUP REG 2 low-high-low. Note that leaving

the SELCTRD bit high will block ALL IREQ events AND will stop

the MUXSEQ counter from counting (this signal is used as the

control to pre-load the MUXSEQ counter from the MUXSEQ

cause an artificial IREQ event when in FIFO mode. Use the

SELCTRD bit to clear this.