User`s guide

Elan Digital Systems Ltd. 22 AD125 USER’S GUIDE
The following examples should clarify this:
MUXSEQ REGISTER CHANNEL SEQUENCE
HEX SINGLE ENDED DIFFERENTIAL
00 A1,A1,A1,A1.... (A1- A5), (A1-A5), (A1-
A5)....
55 A6,A6,A6,A6.... (A10-A14), (A10-A14),
(A10-A14)....
AA A11,A11,A11.... INVALID
FF A16,A16,A16.... INVALID
64 A5,A6,A7,A5,A6,A7.... (A9-A13), (A10-A14), (A11-
A15), (A9-A13), (A10-
A14)....
1B A12,A13,A14,A15,A16
,A1,A2,A12,A13,A14,
A15,A16....
INVALID
0F A16,A1,A16,A1,A16,A
1,A16....
INVALID
18 A9,A10,A11,A12,A13,
A14,A15,A16,A1,A2,A
9,A10,A11...
INVALID
When the AD125 stores the conversion data into the SRAM it also
saves the mux counter value for the conversion in the top four bits of
the 16-bit data word. This provides a useful way of keeping track of
which samples came from which input channel.
The MUX address changes approximately 100ns after the track and
hold enters hold mode for the current conversion.
When the AD125 is running at the maximum sample rate there is
1.9µs available for the MUX and analogue inputs to settle before the
next conversion occurs. To keep 12-bit resolution when scanning
input channels at a high rate requires some careful thought with
regard to the magnitude of the difference in voltage between
successive channels. Large voltage differences causes large step
changes in the analog circuits which take longer to settle to ½LSB
accuracy. If this situation cannot be avoided but full channel scan
rate is required then be prepared to loose some accuracy in the last
few bits of the 12 bit conversion result.