User`s guide

Elan Digital Systems Ltd. 20 AD125 USER’S GUIDE
3.5 OTHER FEATURES
3.5.1 SAMPLE RATE
The SAMPLE RATE is programmed via a 14-bit divider, accessed
as an 8-bit register (DIVLO) and a 6-bit register (DIVHI). The clock
divider runs at 5MHz. Additionally, there is an extra control bit that
allows subtraction of a ¼ clock period from the divider. This is
located in SETUP REG 1 BIT-2 and is called “nTIMING”. The
purpose of this bit is to allow additional frequencies to be obtained
e.g. 571.4KSPS (at the top end).
The calculation for the two data bytes is given by:
nTIMING bit SET:
DIVHI = (round(1/(FSample*200E-9))-2) >> 8);
DIVLO =(round(1/(FSample*200E-9))-2) & 255);
( so FSample = 1/(200E-9 * (DIVHI:DIVLO + 2)) )
nTIMING bit RESET:
DIVHI = (round(1/(FSample*200E-9))-1.75) >> 8);
DIVLO =(round(1/(FSample*200E-9))-1.75) & 255);
( so FSample = 1/(200E-9 * (DIVHI:DIVLO + 1.75)) )
Where FSample is in Hz.
This gives:
FSample min = 305.1Hz (count=0x3FFF)
FSample max = 250KSPS (count=0x12 nTIMING=1 AD132)
500KSPS (count=0x08 nTIMING=1)
or 625KSPS (count=0x06 nTIMING=1 AD1x6 only)
For the AD1x5 and AD1x6 the input bandwidth of the card is
restricted to around 250KHz to aid with anti-aliasing requirements.
For the AD132 it is limited to around 120KHz. If slower sample
rates are used and signals greater than the Nyquist rate are present in
the input signal, some form of off card low-pass filtering may be
required. This filtering can be as simple as placing resistance in line
with the input signal. When adding series resistance, don’t forget
that you will also tend to degrade the card’s accuracy and induce
offset errors due to bias currents etc