User`s guide

Elan Digital Systems Ltd. 16 AD125 USER’S GUIDE
Remember that you must control the RUN and ENTRIG bits
correctly to ensure that the pre-trigger buffer actually holds valid
conversion data: the AD125 could trigger before conversion results
have been written into the whole pre-trigger area of SRAM. The
rule is to set the AD125 into RUN mode but with ENTRIG off, in
software wait a minimum of (t x n) seconds before enabling trigger
(t is the sample period, n is the pre-trigger depth in conversions).
3.3.4 READING THE SRAM DATA
SRAM data is accessed via a single IO port at IOBASE+2. Each
read by the PC will fetch data and decrement the READ POINTER.
If the AD125 has halted after a BURST acquisition then the READ
POINTER must be “released” temporarily to read out the A to D
data. This is achieved by setting SINGLE mode (Bit 7 in SETUP
REG 2). Be sure to return this bit to zero before attempting to do
further BURST acquisitions.
SRAM data can be read as bytes or words. If reading bytes, read
two bytes to make a 16-bit value; the data is stored in the bottom 12
bits. If reading words, read 1 word to get a 16-bit value. The word
wide transfer will be broken into 2 byte wide transfers automatically
by the HOST PC. Pseudo word access throughput is faster than byte
access throughput. The HOST PCMCIA controller should be
configured with an 8-bit wide IO window running from IOBASE to
IOBASE+3 (NOT +2 else word-to-byte conversions may not work
correctly).
Note that the top 4 bits of the SRAM data hold the MUXSEQ count
of the conversion...see section on INPUT MUX CONTROL.