User`s guide

Elan Digital Systems Ltd. 14 AD125 USER’S GUIDE

3.3 AD125 BUFFER ADDRESSING

3.3.1 BUFFER DATA ORDER

The AD125 always writes its A to D conversion samples into the

SRAM buffer. They can be read out directly by the PC software. 2

bytes of data get written to the SRAM for every conversion “event”.

The buffer is organised as follows:

Pointer Address Decreasing →→

7FFF 7FFE 7FFD 7FFC 7FFB 7FFA

Sample

low byte

Sample

high byte

Sample

n+1

low byte

Sample

n+1

high byte

Sample

n+2

low byte

etc etc...

The counters that control the SRAM addressing are 15-bit down

counters that address bytes. When cleared they are set to 7FFFh.

Each read by the PC of a byte of data decrements the READ

POINTER by one. Each conversion event decrements the WRITE

POINTER by two.

3.3.2 CONTROLLING THE SRAM POINTERS

The READ and WRITE pointers are 15 bits in length. They can also

be programmed to be 8,9,10,11,12,13 or 14 bits long if a “shorter”

buffer length is required. To achieve this, write to the CTLEN port

with a 7 bit value. The bits in this byte, referred to as the BUFFLEN

byte, are used to set the buffer length in the following way:

00h→8 bit

01h→9 bit

03h→10 bit

07h→11 bit

0Fh→12 bit

1Fh→13 bit

3Fh→14 bit

7Fh→15 bit

Note: The power up state of the CTLEN port is 00h

To decrement the READ POINTER by one, do a write access to the

DECR port with don’t care data.