ELAN DIGITAL SYSTEMS LTD. LITTLE PARK FARM ROAD, SEGENSWORTH WEST, FAREHAM, HANTS. PO15 5SJ. TEL: (44) (0)1489 579799 FAX: (44) (0)1489 577516 e-mail: support@elan-digital-systems.co.uk website: www.pccard.co.uk AD125 PC-CARD USER’S GUIDE ALSO COVERS AD135, AD126, AD136, AD132, AD121, AD131 AND “MF2xx” SERIES CARDS REVISION HISTORY ISSUE PAGES DATE NOTES 1 2 50 50 30.10.96 06.03.97 3 4 5 50 50 48 06.06.97 17.06.97 26.01.98 6 50 15.07.98 7 43 23.07.98 8 45 04.01.
CONTENTS 1. OVERVIEW..................................................................................................4 1.1 MODEL NAMING CONVENTIONS......................................................................................... 5 2. ABOUT THE AD125 ....................................................................................6 2.1 QUICK THEORY OF SUCCESSIVE APPROXIMATION CONVERTERS ........................ 6 2.2 NOISE..........................................................................
4.5 DIVHI / ADDRCTHI (IR 5)....................................................................................................... 35 4.6 MUXSEQ (IR 6).......................................................................................................................... 36 4.7 TRIGTHRESH (IR 7) ................................................................................................................ 36 4.8 CTLEN (IR 9) ................................................................................
1. OVERVIEW Before using the AD125, take some time to read the section “OPERATIONAL PRECAUTIONS”. The AD125 card is a general purpose Analogue Data Acquisition card with the following features: • 12-bit 0.5MSPS A to D converter (0.625MSPS FOR AD1x6) (0.25MSPS FOR AD132, 0.
1.1 MODEL NAMING CONVENTIONS The AD125 “family” of cards follows these naming conventions: “AD1[X][Y]” for A to D cards “MF2[X][Y]” for Multi-function A to D and D to A cards [X] [Y] “2” ⇒ 8 single ended channels “3” ⇒ 16 single ended channels “1” ⇒ 100KSPS max sample rate “2” ⇒ 250KSPS max sample rate “5” ⇒ 500KSPS max sample rate “6” ⇒ 625KSPS max sample rate Elan Digital Systems Ltd.
2. ABOUT THE AD125 2.1 QUICK THEORY OF SUCCESSIVE APPROXIMATION CONVERTERS The type of converter used in the AD125 approximates the analogue level being applied to its input using a D to A converter and a comparator. The converter starts in “track” mode where it is following the input voltage and applying it to a track and hold amplifier. Once the converter is told to perform a conversion, it holds the current input voltage level on a capacitor while it approximates its value.
that the noise is Gaussian in distribution and is subject to the usual statistical spread in its peaks and troughs from moment to moment. So the converter output looks noisy, or at least more noisy than you might expect. Normally this is not a problem but occasionally some kind of post-processing of the data samples will be required in software. This may mean a simple averaging process over say 10 or more samples, or could be a properly designed digital filter. This will depend on the exact application.
2.3 POSSIBLE SOURCES OF MEASUREMENT ERROR The following is a list of possible error sources that should be considered when taking measurements with the AD125: 1. The offset voltage of the A to D device and the front end electronics will mean that an input voltage of 0V will not produce an output code of 000000000000b. Software could be used to correct for zero-point offset errors by using one of the analogue inputs to the AD125 and tying it to AGND.
inside the AD125 at a “star-point”. All digital front-end circuits use a separate ground trace to the front-end analogue circuits to reduce such switching noise problems on the card itself. The AGND/GND link occurs at the PCMCIA 68-way connector. 6. If using the inputs in differential mode, do not forget to keep the common mode signal within the common mode range of the AD125s inputs. The “best” you can achieve is to ensure that the side is very close to the card’s AGND level.
3. CONTROLLING THE AD125 3.1 ACQUISITION MODES In all modes, the AD125 performs its conversions in around 2.0µs (1.66µs for the AD1x6). The conversion rate is software programmable and is achieved by “spreading-out” the conversions using the PACER clock. 3.1.1 BURST MODE This is the mode intended for transient capture or vibration analysis. Summary: The AD125 is set up with trigger threshold and edge. The READ and WRITE POINTERS are put into a known starting state. The pre-trigger depth is configured.
3.1.2 FIFO MODE This is the mode intended for streaming data into the PC at high speed. Summary: The AD125 takes continuous conversions in this mode. There is no triggering. As soon as software sets RUN to on, the SRAM starts to fill. The PC must empty the SRAM at a rate at least equal to the rate at which it is being filled. An interrupt can be generated at 1/4 or 1/2 full to instruct the PC to fetch the correct amount of data from the buffer. The throughput in this mode is PC speed dependent.
3.2 A to D OUTPUT FORMAT / GAIN SETTING The AD125 produces 2’s complement 12 bit output codes when in Bipolar mode and “true binary” 12 bit codes when in Unipolar mode. Table 3.2-1 summarises the codes. THEORETICAL INPUT LEVEL (F.S. = FULL SCALE) F.S. F.S. - 1LSB .... 0 + 2LSB 0 +1LSB 0 0 - 1LSB 0 - 2LSB .... -F.S. + 1LSB -F.S. AD125 OUTPUT CODE BIPOLAR UNIPOLAR BINARY HEX BINARY HEX 011111111111 7FF 111111111111 FFF 011111111110 7FE 111111111110 FFE .... .... .... ....
20 different input ranges can be achieved with the AD125. The gain is programmed using the top four bits of SETUP REG 1 (GS0..3). The following table summarises the gains and input ranges available: GAIN GS0..3 4 2 4/3 1 4/5 2/3 4/7 1/2 4/9 2/5 4/11 1/3 4/13 2/7 4/15 1/4 0h 1h 2h 3h 4h 5h 6h 7h 8h 9h Ah Bh Ch Dh Eh Fh Elan Digital Systems Ltd. AD125 INPUT VOLTAGE RANGE (volts) BIPOLAR UNIPOLAR ± 0.625 0 → 1.25 ± 1.25 0 → 2.5 ± 1.875 0 → 3.75 ± 2.5 0 → 5.0 ± 3.125 0 → 6.25 ± 3.75 0 → 7.5 ± 4.375 0 → 8.
3.3 AD125 BUFFER ADDRESSING 3.3.1 BUFFER DATA ORDER The AD125 always writes its A to D conversion samples into the SRAM buffer. They can be read out directly by the PC software. 2 bytes of data get written to the SRAM for every conversion “event”. The buffer is organised as follows: Pointer Address Decreasing → 7FFF 7FFE 7FFD Sample Sample Sample n n n+1 low byte high byte low byte 7FFC Sample n+1 high byte 7FFB Sample n+2 low byte 7FFA etc etc...
To decrement the WRITE POINTER by TWO, do a write access to the DECW port with don’t care data. Remember that in FIFO mode, you may get an IREQ when changing the WRITE POINTER through a half or quarter count (just as you would if the AD125 passed these points whilst running at full speed...use the SELCTRD bit to block interrupts whilst manipulating the WRITE POINTER if this is a problem...see section on interrupts). To clear all system counters to 7FFFh do the following: 1.
Remember that you must control the RUN and ENTRIG bits correctly to ensure that the pre-trigger buffer actually holds valid conversion data: the AD125 could trigger before conversion results have been written into the whole pre-trigger area of SRAM. The rule is to set the AD125 into RUN mode but with ENTRIG off, in software wait a minimum of (t x n) seconds before enabling trigger (t is the sample period, n is the pre-trigger depth in conversions). 3.3.
3.4 TRIGGERING 3.4.1 THRESHOLD The AD125 uses an 8-bit 2’s complement OR “true binary” trigger threshold value. This is compared against the top 8-bits of the 12bits of A to D data to decide when to trigger the card. The value loaded into the threshold register MUST be appropriate to the conversion mode selected: 2’s complement for Bipolar, “true binary” for Unipolar.
3.4.2 TRIGGER MODES There are various configurations of trigger on the AD125, they are summarised below: +ET -ET > < TREDGE=1 LVL=0 TRIGGER WHEN I/P TRANSITIONS FROM BELOW Vtrig TO ABOVE Vtrig TREDGE=0 LVL=0 TRIGGER WHEN I/P TRANSITIONS FROM ABOVE Vtrig TO BELOW Vtrig TREDGE=1 LVL=1 TRIGGER WHENEVER I/P IS ABOVE Vtrig TREDGE=0 LVL=1 TRIGGER WHENEVER I/P IS BELOW Vtrig The modes are programmed via SETUP REG 2. The AD125 can also be trigged externally via the nTRIGGER edge connector signal.
3.4.3 ENABLING TRIGGER The AD125 will not trigger unless Bit 1 of SETUP REG 1 is low. This allows software to “arm” the AD125 only when it is appropriate to do so i.e. after some start up condition or when the user has signalled that the system should arm ready to capture an event. Elan Digital Systems Ltd.
3.5 OTHER FEATURES 3.5.1 SAMPLE RATE The SAMPLE RATE is programmed via a 14-bit divider, accessed as an 8-bit register (DIVLO) and a 6-bit register (DIVHI). The clock divider runs at 5MHz. Additionally, there is an extra control bit that allows subtraction of a ¼ clock period from the divider. This is located in SETUP REG 1 BIT-2 and is called “nTIMING”. The purpose of this bit is to allow additional frequencies to be obtained e.g. 571.4KSPS (at the top end).
3.5.2 INPUT MUX CONTROL There are 8 input channels to the AD12x and 16 to the AD13x. The channels can be used either in single ended mode i.e. number of input channels equals 8 (AD12x) or 16 (AD13x) OR they can be set to work in true differential mode giving 4 channels (AD12x) or 8 channels (AD13x). Refer to the pinout table for details of which channels are “differential pairs”. The channels are multiplexed by fault protected muxes at the “front end” of the card.
The following examples should clarify this: MUXSEQ REGISTER CHANNEL SEQUENCE HEX SINGLE ENDED DIFFERENTIAL 00 A1,A1,A1,A1.... 55 A6,A6,A6,A6.... AA FF 64 A11,A11,A11.... A16,A16,A16.... A5,A6,A7,A5,A6,A7.... 1B A12,A13,A14,A15,A16 ,A1,A2,A12,A13,A14, A15,A16.... A16,A1,A16,A1,A16,A 1,A16.... A9,A10,A11,A12,A13, A14,A15,A16,A1,A2,A 9,A10,A11... (A1- A5), (A1-A5), (A1A5).... (A10-A14), (A10-A14), (A10-A14).... INVALID INVALID (A9-A13), (A10-A14), (A11A15), (A9-A13), (A10A14)....
3.5.3 SLEEP MODE The AD125 can be put into a low power SLEEP mode. This effectively shuts down the internal DC-DC converters, oscillator and AtoD converter. The analogue part of the card will not function in this mode. When enabling the card i.e. coming out of SLEEP mode, allow at least 2 seconds for the power to stabilise before taking any measurements. The card powers up in SLEEP mode and enters SLEEP mode after a hard or soft reset.
To actually use interrupts the HOST controller will have to be configured to route the IREQ signal to one of the PC’s interrupt channels. Note that all conditions that cause an interrupt can also be polled for in software; that is, you do not have to use interrupts. This is because the state of the internal Flip-Flop that latches the interrupt state can be read via IODIR REGISTER Bit 4: 0→INTERRUPT PENDING, 1→NO INTERRUPT. The interrupt from the AD125 is latched.
3.5.5 CONFIG OPTION REGISTER The AD125 uses the Config Option Register or COR to enable a particular mode. The COR is at 400h in attribute space and is 8-bits wide read/write. It is organised as follows: BIT0 BIT1 BIT2 BIT3 BIT4 BIT5 BIT6 BIT7 Config value LSB . . . . Config value MSB Not used Apply internal RESET when set The config values (6 bit) are as follows: COR Config value 0 1 5 Elan Digital Systems Ltd.
3.5.6 DIGITAL IO There are 8 digital IO lines which can be used for general control / monitoring. The bottom 4 bits of the IODIR register are used to configure the IOPINs as inputs or outputs. The grouping is as follows: BIT0 BIT1 BIT2 BIT3 DIRECTION OF IOPIN1 DIRECTION OF IOPIN2 DIRECTION OF IOPIN3&4 DIRECTION OF IOPIN5,6,7&8. Setting a bit high enables the pin/group of pins as outputs.
3.6 DAC PROGRAMMING The DACs on the MF series are loaded serially using the upper four digital I/O lines (which are no longer accessible on the MF series).
updates at a low rate. Due to the high overhead involved with loading DAC codes, DAC update rates of a few Hz can be realised. By setting the interrupt configuration of the FIFO run mode of the card this interrupt can occur i) every sample ii) every quarter buffer (i.e. every 4096/Fsample seconds) iii) every half buffer (i.e. every 8192/Fsample seconds).
4. AD125 REGISTER INTERFACE The AD125 decodes the incoming PCMCIA interface. It maps the CIS EPROM to 0-3FF,800-BFF etc. in attribute space. The range 400-7FF is occupied by the PCMCIA config option register inside the AD125 (it repeats every byte). Both the CIS and COR are always active. The COR is used as a master enable, as defined by PCMCIA 2.01. That is, when a valid config is written in bits0..5 the card's I/O interface may function. Until this has happened, the card's I/O interface is disabled.
The following table shows the indexes of the various registers in the AD125 (all are 8-bits unless stated): IR 0 1 2 3 4 5 6 7 8 9 A B C D E F DR write SETUP REG 1 (8-BIT) SETUP REG 2 IODATA IODIR (4-BIT) DIVLO DIVHI (6-BIT) MUXSEQ TRIGTHRESH N/U CTLEN N/U N/U N/U DECR DECW CLRCT DR read SETUP REG 1 (8-BIT) SETUP REG 2 IODATA IODIR(6-BIT) ADDRCTLO ADDRCTHI N/U N/U SETUP REG 1 (8-BIT) SETUP REG 2 IODATA IODIR(6-BIT) ADDRCTLO ADDRCTHI N/U N/U Port Index Allocations in the AD125 NOTE 1.
4.0 SETUP REG 1 (IR 0) BIT 0 RESET STATE FUNCTION WRITE nRUN READ nRUN 1 nENTRIG 1 nTIMING 1 nSLEEP 0 GS0 0 GS1 GS2 GS3 0 0 0 Set low to start the AD125 taking conversions or to start a SINGLE conversion. 1 nENTRIG Set low to enable triggering i.e. ARM the AD125 (BURST mode only). 2 nTIMING Set low to enable a ¼ clock period subtraction from the PACER divider. 3 nSLEEP Set low to put AD125 into low power SLEEP mode.
4.1 SETUP REG 2 (IR 1) BIT 0 RESET STATE FUNCTION WRITE IBITSEL0 READ IBITSEL0 0 IBITSEL1 0 BIPOLAR 0 SINGLEEND 0 TREDGE 0 LVL 0 SELCTRD 0 SINGLE 0 See IBITSEL1. 1 IBITSEL1 MSBit of 2-bit interrupt select: 00: Interrupt when buffer full 01: Interrupt every ½buffer full 10: Interrupt every ¼ buffer full 11: Interrupt every conversion Only applies in FIFO mode.
4.
4.3 IODIR (IR 3) BIT 0 RESET STATE FUNCTION WRITE IOPIN0DIR READ IOPIN0DIR 0 IOPIN1DIR 0 IOPIN2&3DIR 0 IOPIN4,5,6,7DIR or WFGEN 0 nIREQ 0 Set high to enable as OUTPUT 1 IOPIN1DIR Set high to enable as OUTPUT 2 IOPIN2&3DIR Set high to enable as OUTPUTS 3 IOPIN4,5,6,7DIR Set high to enable as OUTPUTS. On MF series the upper four IOs are always outputs and this bit changes function to become WFGEN which enables DAC waveform generation mode when high.
4.4 DIVLO / ADDRCTLO (IR 4) BIT 0 1 2 3 4 5 6 7 RESET STATE FUNCTION WRITE DIV0 DIV1 DIV2 DIV3 DIV4 DIV5 DIV6 DIV7 READ ADDRCT0 ADDRCT1 ADDRCT2 ADDRCT3 ADDRCT4 ADDRCT5 ADDRCT6 ADDRCT7 LOW 8-BIT WORD OF 14-BIT CLOCK DIVIDER. SEE ALSO THE “TIMING” BIT IN SETUP REG 1. LOW 8-BIT WORD OF 16-BIT READ OR WRITE POINTER. - 4.
4.6 MUXSEQ (IR 6) BIT 0 RESET STATE FUNCTION WRITE MUXSEQ0 READ 0 (start address LSB) 1 2 3 MUXSEQ1 MUXSEQ2 MUXSEQ3 0 0 0 (start address MSB) 4 MUXSEQ4 0 (end address LSB) 5 6 7 MUXSEQ5 MUXSEQ6 MUXSEQ7 0 0 0 (end address MSB) 8-BIT VALUE USED TO CONTROL INPUT MUX SEQUENCING. 4.
4.8 CTLEN (IR 9) BIT 0 1 2 3 4 5 6 7 RESET STATE FUNCTION WRITE CTLEN0 CTLEN1 CTLEN2 CTLEN3 CTLEN4 CTLEN5 CTLEN6 READ 0 0 0 0 0 0 0 0 7-BIT VALUE TO CONTROL ACTIVE LENGTH OF READ AND WRITE POINTERS. ALSO USED TO FORCE A PARTIAL RESET OF BOTH READ AND WRITE POINTERS. BIT-MAPPED: 0x7F SETS 15-BIT, 0x3F-14, 0x1F-13, 0x0F-12, 0x07-11, 0x03-10, 0x01-9, 0x00-8-BIT. MUST BE 15-BIT FOR FIFO MODE. 4.
4.10 DECW (IR E) BIT 0 1 2 3 4 5 6 7 RESET STATE FUNCTION WRITE X X X X X X X X READ X X X X X X X X - ANY READ OR WRITE ACCESS TO THIS PORT WILL DECREMENT THE WRITE POINTER BY TWO. 4.11 CLRCT (IR F) BIT 0 1 2 3 4 5 6 7 RESET STATE FUNCTION WRITE X X X X X X X X READ X X X X X X X X - ANY READ OR WRITE ACCESS TO THIS PORT WILL SET THE READ & WRITE POINTERS TO 0x7FFF AND WILL PRE_LOAD THE MUX COUNTER WITH THE MUXSEQ START ADDRESS.
5. HARDWARE SPECIFICATION 5.1 PINOUT MATING CONNECTOR TYPE: HIROSE NX30TA-32PAA + NX-32TA-CV1 + NX-32T-BS PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 NAME A1 A5 A2 A6 A3 A7 A4 A8 A9 (AD135/6 ONLY) A13 (AD135/6 ONLY) A10 (AD135/6 ONLY) A14 (AD135/6 ONLY) A11 (AD135/6 ONLY) A15 (AD135/6 ONLY) A12 (AD135/6 ONLY) A16 (AD135/6 ONLY) AGND GND IOPIN0 IOPIN1 IOPIN2 IOPIN3 IOPIN4/DAC1 0→ →2.5V IOPIN5/DAC1 ±10V IOPIN6/DAC2 0→ →2.
5.2 ANALOGUE • ALL PARAMETERS @ 25°C (UNLESS STATED) • “S/W” DENOTES SOFTWARE CONFIGURABLE • SPECIFICATIONS LISTED FOR AD1xx ALSO APPLY TO MF2xx EQUIVALENT AD125, AD126, AD121 INPUT CHANNELS: 8 SINGLE ENDED OR 4 DIFFERENTIAL (S/W) AD135, AD136, AD132, AD131 INPUT CHANNELS: 16 SINGLE ENDED OR 8 DIFFERENTIAL (S/W) INPUT RANGES: GAIN ACCURACY: UNIPOLAR: 0 to 1.25V, 2.5V, 3.75V, 5.0V, 6.25V, 7.5V, 8.75V, 10.0V (S/W) BIPOLAR: +/-0.625V, 1.25V, 1.875V, 2.5V, 3.125V, 3.75V, 4.375V, 5.0V, 5.625V, 6.25V, 6.
AD1x1, AD1x2 INPUT IMPEDANCE: ≈ (4000 + 109 / Fin) Ω (SINGLE ENDED) ! Avoid significant source impedance if you are digitising AC components with relatively high frequencies. To avoid attenuation > 1LSB the source impedance should be 4096 times less than the above calculated value. The frequency dependent nature of the input impedance can be used to affect extra anti-aliasing by deliberately adding source impedance to your signal and so attenuating higher frequencies. At DC the input impedance is >10Meg.
“”Zero point at gain xxx in Unipolar Mode “” Full scale point at gain xxx in Unipolar Mode “” Zero point at gain xxx in Bipolar Mode “” Full scale point at gain xxx in Bipolar Mode Zero point is defined in two ways : i) for Unipolar mode it is the voltage applied to the card that causes the ADC reading to be +½LSB±¼LSB when averaged over 1000 readings.
5.3 DIGITAL ALL PARAMETERS @ 25°C SAMPLE BUFFER: ACQUISITION MODES: FIFO THROUGHPUT: 32768 x 8 BITS (16K SAMPLES) BURST, FIFO, SINGLE SHOT > 500KSPS (PC SPEED DEPENDENT) DIGITAL I/O CHANS: DIGITAL I/O DRIVE: I/O CONFIGURATIONS: 8 CHANNELS (AD) OR 4 (MF) BIT-MAPPED, PROG AS I/P OR O/P 4mA TYP TO TTL LEVELS.
6. SOFTWARE 6.1 UNIVERSAL DRIVER The PCCARDGO “universal driver” is used to act as a surrogate Card Services client for an end user application. This device driver simplifies greatly the enumeration process and configuration management task for your application. The driver is supplied on the diskette provided. Please refer to PCCARDGO.DOC for further information. 6.2 C SOURCE CODE On the diskette provided are several .C and .
7. OPERATIONAL PRECAUTIONS Unless otherwise stated, all voltage levels are referenced to the AD125’s DIGITAL GROUND PIN. • Don’t leave active signals connected to the digital IOPINS that are capable of sourcing more than a few mA whilst the AD125 itself is unpowered. This could lead to “reverse powering” the card via its inputs which can cause latch-up and destruction of internal cmos devices.
