User`s manual

Software Manual • EKF Intelligent I/O Controller Family On CompactPCI
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Inbound Message Register 0 (IMR0)
Bit Access Description
31:00 Read/Write Inbound Message Word.
The Outbound Message Register 0 (OMR0) is used to send messages from the controller to
the host. When OMR0 is written by the controller firmware, an interrupt is requested on the
CompactPCI bus. Interrupt generation can be disabled by setting bit 0 in the Outbound
Interrupt Mask Register OIMR.
Outbound Message Register 0 (OMR0)
Bit Access Description
31:00 Read/Write Outbound Message Word generated by the controller.
The Outbound Interrupt Status Register (OISR) records the status of the PCI interrupts
generated by the MU. If the firmware has send a message to the host this is indicated by the
fact that bit 0 of the OISR is set. Interrupt generation may be masked by setting the
corresponding bits in the Outbound Interrupt Mask Register (OIMR). All other bits in OISR
will never be set by the controller.
Outbound Interrupt Status Register (OISR)
Bit Access Description
31:08 Read Only Reserved (Read as 0)
7 Read Only PCI Doorbell Interrupt D.
6 Read Only PCI Doorbell Interrupt C.
5 Read Only PCI Doorbell Interrupt B.
4 Read Only PCI Doorbell Interrupt A.
3 Read Only Outbound Post Queue Interrupt.
2 Read Only Outbound Doorbell Interrupt.
1 Read/Clear Outbound Message 1 Interrupt.
0 Read/Clear Outbound Message 0 Interrupt - set by the MU when the OMR0 is written by the
i960 processor. Clearing this by writing a one to it clears the interrupt request.
The Outbound Interrupt Mask Register (OIMR) is used to mask undesirable interrupts that
may be generated by the MU. Each bit set in OIMR will disable the corresponding interrupt
source. Note, that this register defaults to all bits cleared after reset, thus all interrupts are
enabled.