User`s manual

Software Manual • EKF Intelligent I/O Controller Family On CompactPCI
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window occupied by the PCI device. Others are filled by the system controller’s BIOS, e.g.
the primary inbound ATU base address register PIABAR.
To identify a board the firmware writes the following subsystem IDs and class codes to the
corresponding registers:
Subsystem and Subvendor IDs
Board Subvendor ID Subsystem ID Base Class Code Sub Class Code
CG1-RADIO 0xE4BF 0x1010 0x07
1
) 0x02
3
)
CU1-CHORUS 0xE4BF 0x1040 0x07
1
) 0x02
3
)
CU2-QUARTET 0xE4BF 0x1020 0x07
1
) 0x02
3
)
CX1-BAND 0xE4BF 0x3100 0x0C
2
) 0x09
4
)
Notes:
1
) Base Class Code for Simple Communication Controllers
2
) Base Class Code for Serial Bus Controllers
3
) Sub Class Code for Multiport Serial Controller
4
) Sub Class Code for CANbus Controller
The Messaging Unit appears as a set of memory mapped registers, starting at the base
address defined in the register PIABAR (offset 0x10 in configuration space of function 1).
The MU consists of a fixed header defined by the i960 processor (first 4KByte) and a
following part defined by the software interface.
Read and write accesses of byte, short or long size are possible although there are a few
registers containing bits that are read only or read/clear (e.g. the interrupt status registers).
The following table shows the structure of the MU, the address offset shown is with respect
to the base address. Registers that are meaningful for the software interface are marked
light blue/italic:
Structure of the Messaging Unit Registers
MU Register Name Member Name
1
) Address Offset
APIC Register Select Register ARSR 0x0000
Reserved 0x0004
APIC Window Register AWR 0x0008
Reserved 0x000C
Inbound Message Register 0 IMR0 0x0010
Inbound Message Register 1 IMR1 0x0014
Outbound Message Register 0 OMR0 0x0018
Outbound Message Register 1 OMR1 0x001C
Inbound Doorbell Register IDR 0x0020