User's Manual

EWB160031M User manual
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7. Reference Design
In order to achieve minimal power consumption, users may, under all types of operational modes,
control the power modules in the control chip in OPL1600 chip of internal high-performance Buck
& LDO DC-DC Converter. The system power, with input of decoupled capacitor from external
battery power originated from VDD_BAT (pin 8), reduces noise with in-chip Buck DC-DC
Converter, respectively in.
The OPL1600 is divided into four power domains, including analog, Power Management Subsystem
(PMS), core, and retention power domains. The retention domain includes SRAM, IOPAD control
logic and register files.
The analog and core domains can be powered off, and the retention domain power reduced to
retention voltage to minimize the current of SRAM during the sleep mode. The sleep mode wakeup
event can come from external event GPIOs and internal timer event.In addition, the OPL1600 can be
put into lowest power consumption mode by driving EN pin to ground.
PWR_EN is used to control some basic analog bias blocks. Pull this pin low can minimize the leakage
current. To avoid race condition and make sure power up sequence is normal, PWR_EN must not rise
with VBAT at the same time. A simple RC circuit connect to VBAT can provide enough delay if
PWR_EN is not controlled separately.