Datasheet

35
Using BIOS
Press <Esc> to return to the Advanced Chipset Features page.
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• CAS# latency (Tcl): This item determines the operation of DDR SDRAM
memory CAS (column address strobe). It is recommended that you leave this
item at the default value. The 2T setting requires faster memory that specifi-
cally supports this mode.
User Config mode(Auto)
This item has the capacity to automatically detect all of the fllowing fieldsdefault values. This
item is set to [Auto] by default. When setting to[Manual], the following items are adjustable.
• 1T/2T Memory Timing (Auto): Users please note that this item appears
only if CPU after CG version is installed. CPU before CG version will support
1T Memory Timing only. This item enables you to specify the waiting time for
the CPU to issue the next command after issuing the command to the DDR
memory. We recommend that you leave this item at the default value.
• Read Preamble value (6ns): This item allows you to set Read Preamble
value from 2ns, to 9.5ns, and it is specified in units of 0.5ns.
• Async Latency value (7ns): This item allows you to set Async Latency
value from 2ns to 11ns, and it is specified in units of 1 ns.
MTRR mapping mode (Continuous)
Use the MTRR (Memory Type Range Registers) technology to control the cache memory.
LDT & PCI Bus Control (Press Enter)
Scroll to this item and press <Enter> to view the following screen:
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Upstream LDT Bus Width [16 bit]
Downstream LDT Bus Width [16 bit]
LDT Bus Frequency [800 MHz]
PCI1 Master 0 WS Write [Enabled]
PCI2 Master 0 WS Write [Enabled]
PCI1Post Write [Enabled]
PCI2 Post Write [Enabled]
PCI Delay Transaction [Disabled]
Item Help
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Menu Level
Phoenix-AwardBIOS CMOS Setup Utility
LDT & PCI Bus Control
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F5:Previous Values F6:Fail-Safe Defaults F7:Optimized Defaults
: Move Enter: Select +/-/PU/PD:Value F10:Save ESC:Exit F1: General Help
Upstream LDT Bus Width (16 bit)
This item allows users to manually adjust the upstream LDT bus width to be 8 bit or 16 bit.
Downstream LDT Bus Width (16 bit)
This item allows users to manually adjust the downstream LDT bus width to be 8 bit or 16 bit.
LDT Bus Frequency (800MHz)
This option allows you to specify the maximum operating frequency for the LDT transmitter clock.
PCI1/2 Master 0 WS Write (Enabled)
When enabled, writes to the PCI bus are executed with zero wait states, providing faster datatransfer.