Specifications

38
Using BIOS
M.I.B. II (MB Intelligent BIOS II)
This page enables you to set the clock speed and system bus for your system. The
clock speed and system bus are determined by the kind of processor you have in-
stalled in your system.
CMOS Setup Utility - Copyright (C) 1985-2008, American Megatrends, Inc.
M.I.B.II (MB Intelligent BIOS II)
Help Item
Intel (R) Core (TM) 2 Quad CPU Q8200 @ 2.33 GHz
Ratio Status: Unlocked (Min: 06, Max: 07)
Ratio Actual Value: 7
Base CPU Frequency : 333MHz
Base Memory Frequency : 1333MHz
CPU Core : 1.216 V
VNB : 1.184 V
VDIMM : 1.552 V
CPU VTT : 1.104 V
Performance Level Standard
DRAM Frequency Auto
Configure DRAM Timing by SPD Enabled
DRAM Command Rate Auto
CPU Over-clocking Func.: Disabled
Auto Detect DIMM/PCI Clk Enabled
Spread Spectrum Enabled
CPU Voltage Disabled
NB Voltage
+ 0.055V
DIMM Voltage Disabled
CPU VTT Voltage 1.11V
: Move F10: Save ESC: Exit
+/-/: Value
Enter : Select
F9: Load Default Settings
F1:General Help
mnlk
Standard
Enhanced
Options
Configure DRAM Timing by SPD (Enabled)
When this item is set to enable, the DDR timing is configured using SPD. SPD (Serial
Presence Detect) is located on the memory modules, BIOS reads information coded
in SPD during system boot up.
DRAM Frequency (Auto)
This item enables users to adjust the DRAM frequency. The default setting is auto and
we recommend users leave the setting unchanged. Modify it at will may cause the
system to be unstable.
CPU Over-clocking Func. (Disabled)
This item decides the CPU over-clocking function installed in yoursystem. If the
over-clocking fails, please turn off the system power. And then, hold the PageUp key
(similar to the Clear CMOS function) and turn on the power, the BIOS will recover
the safe default.
Auto Detect DIMM/PCI Clk (Enabled)
When this item is enabled, BIOS will disable the clock signal of free DIMM/PCI slots.
Performance Level (Standard)
This item shows the performance level of the components, the options are: Standard
and Enhanced.
DRAM Command Rate (Auto)
This item specifies the rate of the DRAM Command.