Product Specs

31 SPIM — Serial peripheral interface master with
EasyDMA
Page
283
//replace 'Channel' below by the specific data channel you want to use,
// for instance 'NRF_SPIM->RXD', 'NRF_TWIM->RXD', etc.
Channel.MAXCNT = BUFFER_SIZE;
Channel.PTR = &MyArrayList;
Channel.PTR = &MyArrayList
Note: addresses are
assuming that
sizeof(buffer[n]) is one byte
0x20000000 : MyArrayList[0]
0x20000004 : MyArrayList[1]
0x20000008 : MyArrayList[2]
Figure 70: EasyDMA array list
31.3 SPI master transaction sequence
An SPI master transaction consists of a sequence started by the START task followed by a number of
events, and finally the STOP task.
An SPI master transaction is started by triggering the START task. The ENDTX event will be generated
when the transmitter has transmitted all bytes in the TXD buffer as specified in the TXD.MAXCNT register.
The ENDRX event will be generated when the receiver has filled the RXD buffer, i.e. received the last
possible byte as specified in the RXD.MAXCNT register.
Following a START task, the SPI master will generate an END event when both ENDRX and ENDTX have
been generated.
The SPI master is stopped by triggering the STOP task. A STOPPED event is generated when the SPI
master has stopped.
If the ENDRX event has not already been generated when the SPI master has come to a stop, the SPI
master will generate the ENDRX event explicitly even though the RX buffer is not full.
If the ENDTX event has not already been generated when the SPI master has come to a stop, the SPI
master will generate the ENDTX event explicitly even though all bytes in the TXD buffer, as specified in the
TXD.MAXCNT register, have not been transmitted.
The SPI master is a synchronous interface, and for every byte that is sent, a different byte will be received at
the same time; this is illustrated in Figure 71: SPI master transaction on page 284.
buffer[0]
buffer[1]
buffer[2]
buffer[3]
buffer[0]
buffer[1]
buffer[2]
buffer[3]
buffer[0]
buffer[1]
buffer[2]
buffer[3]