Specifications

February 2015 IS29GL_128S_01GS_00_Rev.A GL-S MirrorBit
®
Family 89
Data Sheet
10.4.3 Alternate CE# Controlled Write Operations
Note:
1. Not 100% tested.
Figure 10.19 Back to Back (CE#) Write Operation Timing Diagram
Table 10.9 Alternate CE# Controlled Write Operations
Parameter
Description
V
IO
= 2.7V to
V
CC
V
IO
= 1.65V
to V
CC
Unit
JEDEC Std
t
AVAV
t
WC
Write Cycle Time (Note 1) Min 60 ns
t
AVWL
t
AS
Address Setup Time Min 0 ns
t
ASO
Address Setup Time to OE# Low during toggle bit polling Min 15 ns
t
WLAX
t
AH
Address Hold Time Min 45 ns
t
AHT
Address Hold Time From CE# or OE# High during toggle
bit polling
Min 0 ns
t
DVWH
t
DS
Data Setup Time Min 30 ns
t
WHDX
t
DH
Data Hold Time Min 0 ns
t
CEPH
CE# High during toggle bit polling Min 20 ns
t
0EPH
OE# High during toggle bit polling Min 20 ns
t
GHEK
t
GHEL
Read Recovery Time Before Write
(OE# High to WE# Low)
Min 0 ns
t
WLEL
t
WS
WE# Setup Time Min 0 ns
t
ELWH
t
WH
WE# Hold Time Min 0 ns
t
ELEH
t
CP
CE# Pulse Width Min 25 ns
t
EHEL
t
CPH
CE# Pulse Width High Min 20 ns
Amax-A0
CE#
OE#
WE#
DQ15-DQ0
tDS tDH
tAS
tAH
tWC
tCP tCPH
tWS tWH