Specifications

88 GL-S MirrorBit
®
Family IS29GL_128S_01GS_00_Rev.A February 2015
Data Sheet
Figure 10.16 Data# Polling Timing Diagram (During Embedded Algorithms)
Note:
1. VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle.
Figure 10.17 Toggle Bit Timing Diagram (During Embedded Algorithms)
Note:
1. DQ6 will toggle at any read address while the device is busy. DQ2 will toggle if the address is within the actively erasing sector.
Figure 10.18 DQ2 vs. DQ6 Relationship Diagram
Note:
1. The system may use OE# or CE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within the erase-suspended sector.
WE#
CE#
OE#
High Z
t
OE
High Z
DQ7
DQ6–DQ0
RY/BY#
t
BUSY
Complement
Tr ue
Addresses
VA
t
OEH
t
CE
t
CH
t
OH
t
DF
VA VA
Status Data
Complement
Valid Data
Valid Data
t
ACC
t
RC
Status Data
Tr ue
OE#
CE#
WE#
Addresses
t
OEH
t
DH
t
AHT
t
ASO
t
OEPH
t
OE
Valid Data
(first read) (second read) (stops toggling)
t
CEPH
t
AHT
t
AS
DQ2 and DQ6 Valid Data
Valid
Status
Valid
Status
Valid
Status
RY/BY#
Enter
Erase
Erase
Erase
Enter Erase
Suspend Program
Erase Suspend
Read
Erase Suspend
Read
Erase
WE#
DQ6
DQ2
Erase
Complete
Erase
Suspend
Suspend
Program
Resume
Embedded
Erasing