Specifications

February 2015 IS29GL_128S_01GS_00_Rev.A GL-S MirrorBit
®
Family 87
Data Sheet
Figure 10.14 Program Operation Timing Diagram
Note:
1. PA = program address, PD = program data, D
OUT
is the true data at the program address.
Figure 10.15 Chip/Sector Erase Operation Timing Diagram
Note:
1. SA = sector address (for sector erase), VA = valid address for reading status data.
OE#
WE#
CE#
Data
Addresses
t
DS
t
AH
t
DH
t
WP
PD
t
WHWH1
t
WC
t
AS
t
WPH
555h
PA PA
Read Status Data (last two cycles)
A0h
t
CS
Status
D
OUT
Program Command Sequence (last two cycles)
RY/BY#
t
RB
t
BUSY
t
CH
PA
OE#
CE#
Addresses
WE#
Data
2AAh SA
t
AH
t
WP
t
WC
t
AS
t
WPH
555h for chip erase
10 for Chip Erase
t
DS
t
CS
t
DH
t
CH
t
WHWH2
VA
VA
Erase Command Sequence (last two cycles)Read Status Data (last two cycles)
RY/BY#
t
RB
t
BUSY
30h
In
Progress
Complete
55h