Specifications

86 GL-S MirrorBit
®
Family IS29GL_128S_01GS_00_Rev.A February 2015
Data Sheet
Figure 10.13 Read to Write (CE# Toggle) Operation Timing Diagram
Notes:
1. Not 100% tested.
2. Upon the rising edge of WE#, must wait t
SR/W
before switching to another address.
3. See Table 5.4 on page 46 and Table 5.5 on page 47 for specific values.
Table 10.8 Erase/Program Operations
Parameter
Description
V
IO
= 2.7V
to V
CC
V
IO
= 1.65V
to V
CC
Unit
JEDEC Std
t
WHWH1
t
WHWH1
Write Buffer Program Operation Typ (Note 3) µs
Effective Write Buffer Program Operation per Word Typ (Note 3) µs
Program Operation per Word or Page Typ (Note 3) µs
t
WHWH2
t
WHWH2
Sector Erase Operation (Note 1) Ty p (Note 3) ms
t
BUSY
Erase/Program Valid to RY/BY# Delay Max 80 ns
t
SR/W
Latency between Read and Write operations (Note 2) Min 10 ns
t
ESL
Erase Suspend Latency Max (Note 3) µs
t
PSL
Program Suspend Latency Max (Note 3) µs
t
RB
RY/BY# Recovery Time Min 0 µs
Amax-A0
CE#
OE#
WE#
DQ15-DQ0
tACC
tOE
tCE
tAS
tCS
tDS
tAH
tDH
tWP
tCH
tOH
tOH
tOH
tDF
tDF
tGHWL