Specifications

February 2015 IS29GL_128S_01GS_00_Rev.A GL-S MirrorBit
®
Family 79
Data Sheet
10.3.2 Hardware (Warm) Reset
During Hardware Reset (t
RPH
) the device will draw I
CC5
current.
When RESET# continues to be held at V
SS
, the device draws CMOS standby current (I
CC4
). If RESET# is
held at V
IL
, but not at V
SS
, the standby current is greater.
If a Cold Reset has not been completed by the device when RESET# is asserted Low after t
VCS
, the Cold
Reset# EA will be performed instead of the Warm RESET#, requiring t
VCS
time to complete.
See Figure 10.4, Hardware Reset on page 79.
After the device has completed POR and entered the Standby state, any later transition to the Hardware
Reset state will initiate the Warm Reset Embedded Algorithm. A Warm Reset is much shorter than a Cold
Reset, taking tens of µs (t
RPH
) to complete. During the Warm Reset EA, any in progress Embedded Algorithm
is stopped and the EAC is returned to its POR state without reloading EAC algorithms from non-volatile
memory. After the Warm Reset EA completes, the interface will remain in the Hardware Reset state if
RESET# remains Low. When RESET# returns High the interface will transit to the Standby state. If RESET#
is High at the end of the Warm Reset EA, the interface will directly transit to the Standby state.
If POR has not been properly completed by the end of t
VCS
, a later transition to the Hardware Reset state will
cause a transition to the Power-on Reset interface state and initiate the Cold Reset Embedded Algorithm.
This ensures the device can complete a Cold Reset even if some aspect of the system Power-On voltage
ramp-up causes the POR to not initiate or complete correctly. The RY/BY# pin is Low during cold or warm
reset as an indication that the device is busy performing reset operations.
Hardware Reset is initiated by the RESET# signal going to V
IL
.
Figure 10.4 Hardware Reset
RESET#
CE#
tRP
tRPH
tRH
tCEH