Specifications

78 GL-S MirrorBit
®
Family IS29GL_128S_01GS_00_Rev.A February 2015
Data Sheet
10.3 Power-On Reset (POR) and Warm Reset
Normal precautions must be taken for supply decoupling to stabilize the V
CC
and V
IO
power supplies. Each
device in a system should have the V
CC
and V
IO
power supplies decoupled by a suitable capacitor close to
the package connections (this capacitor is generally on the order of 0.1 µF).
Notes:
1. Not 100% tested.
2. Timing measured from V
CC
reaching V
CC
minimum and V
IO
reaching V
IO
minimum to V
IH
on Reset and V
IL
on CE#.
3. RESET# Low is optional during POR. If RESET is asserted during POR, the later of t
RPH
, t
VIOS
, or t
VCS
will determine when CE# may go
Low. If RESET# remains Low after t
VIOS
, or t
VCS
is satisfied, t
RPH
is measured from the end of t
VIOS
, or t
VCS
. RESET must also be High
t
RH
before CE# goes Low.
4. V
CC
 V
IO
- 200 mV during power-up.
5. V
CC
and V
IO
ramp rate can be non-linear.
6. Sum of t
RP
and t
RH
must be equal to or greater than t
RPH.
10.3.1 Power-On (Cold) Reset (POR)
During the rise of power supplies the V
IO
supply voltage must remain less than or equal to the V
CC
supply
voltage. V
IH
also must remain less than or equal to the V
IO
supply.
The Cold Reset Embedded Algorithm requires a relatively long, hundreds of µs, period (t
VCS
) to load all of the
EAC algorithms and default state from non-volatile memory. During the Cold Reset period all control signals
including CE# and RESET# are ignored. If CE# is Low during t
VCS
the device may draw higher than normal
POR current during t
VCS
but the level of CE# will not affect the Cold Reset EA. CE# or OE# must transition
from High to Low after t
VCS
for a valid read or write operation. RESET# may be High or Low during t
VCS
. If
RESET# is Low during t
VCS
it may remain Low at the end of t
VCS
to hold the device in the Hardware Reset
state. If RESET# is High at the end of t
VCS
the device will go to the Standby state.
When power is first applied, with supply voltage below V
RST
then rising to reach operating range minimum,
internal device configuration and warm reset activities are initiated. CE# is ignored for the duration of the POR
operation (t
VCS
or t
VIOS
). RESET# Low during this POR period is optional. If RESET# is driven Low during
POR it must satisfy the Hardware Reset parameters t
RP
and t
RPH
. In which case the Reset operations will be
completed at the later of t
VCS
or t
VIOS
or t
RPH
.
During Cold Reset the device will draw I
CC7
current.
Figure 10.3 Power-Up Diagram
Table 10.2 Power ON and Reset Parameters
Parameter Description Limit Value Unit
t
VCS
V
CC
Setup Time to first access (Notes 1, 2)Min300µs
t
VIOS
V
IO
Setup Time to first access (Notes 1, 2)Min300µs
t
RPH
RESET# Low to CE# Low Min 35 µs
t
RP
RESET# Pulse Width Min 200 ns
t
RH
Time between RESET# (High) and CE# (low) Min 50 ns
t
CEH
CE# Pulse Width High Min 20 ns
VCC
VIO
RESET#
CE#
tRH
tVIOS
tVCS
tCEH