Specifications

70 GL-S MirrorBit
®
Family IS29GL_128S_01GS_00_Rev.A February 2015
Data Sheet
8.5.2 Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on WE# will not initiate a write cycle.
8.5.3 Logical Inhibit
Write cycles are inhibited by holding OE# at V
IL
, or CE# at V
IH
, or WE# at V
IH
. To initiate a write cycle, CE#
and WE# must be Low (V
IL
) while OE# is High (V
IH
).