Specifications

February 2015 IS29GL_128S_01GS_00_Rev.A GL-S MirrorBit
®
Family 65
Data Sheet
Hardware Interface
7. Signal Descriptions
7.1 Address and Data Configuration
Address and data are connected in parallel (ADP) via separate signal inputs and I/Os.
7.2 Input/Output Summary
7.3 Versatile I/O Feature
The maximum output voltage level driven by, and input levels acceptable to, the device are determined by the
V
IO
power supply. This supply allows the device to drive and receive signals to and from other devices on the
same bus having interface signal levels different from the device core voltage.
Table 7.1 I/O Summary
Symbol Type Description
RESET# Input
Hardware Reset. At V
IL
, causes the device to reset control logic to its standby state, ready
for reading array data.
CE# Input Chip Enable. At V
IL
, selects the device for data transfer with the host memory controller.
OE# Input
Output Enable. At V
IL
, causes outputs to be actively driven. At V
IH
, causes outputs to be
high impedance (High-Z).
WE# Input
Write Enable. At V
IL
, indicates data transfer from host to device. At V
IH
, indicates data
transfer is from device to host.
A
MAX
-A0 Input
Address inputs.
A25-A0 for IS29GL01GS
A24-A0 for IS29GL512S
A23-A0 for IS29GL256S
A22-A0 for IS29GL128S
DQ15-DQ0 Input/Output Data inputs and outputs
WP# Input
Write Protect. At V
IL
, disables program and erase functions in the lowest or highest address
64-kword (128-kB) sector of the device. At V
IH
, the sector is not protected. WP# has an
internal pull up; When unconnected WP# is at V
IH
.
RY/BY# Output - open drain
Ready/Busy. Indicates whether an Embedded Algorithm is in progress or complete. At V
IL
,
the device is actively engaged in an Embedded Algorithm such as erasing or programming.
At High-Z, the device is ready for read or a new command write - requires external pull-up
resistor to detect the High-Z state. Multiple devices may have their RY/BY# outputs tied
together to detect when all devices are ready.
V
CC
Power Supply Core power supply
V
IO
Power Supply Versatile IO power supply.
V
SS
Power Supply Power supplies ground
NC No Connect
Not Connected internally. The pin/ball location may be used in Printed Circuit Board (PCB)
as part of a routing channel.
RFU No Connect
Reserved for Future Use. Not currently connected internally but the pin/ball location should
be left unconnected and unused by PCB routing channel for future compatibility. The pin/ball
may be used by a signal in the future.
DNU Reserved
Do Not Use. Reserved for use by ISSI. The pin/ball is connected internally. The input has an
internal pull down resistance to V
SS
. The pin/ball can be left open or tied to V
SS
on the PCB.